Dma Controller Interface; Overview; Signals - Intel PXA27 Series Design Manual

DMA Controller Interface

This chapter describes the procedures for interfacing the DMA controller of the Intel
Processor Family (PXA27x processor) with companion chips using the fly-by and flow-through
DMA transfer.
5.1

Overview

The PXA27x processor contains a DMA controller that transfers data to and from the memory
system in response to requests generated by peripherals or companion chips. These peripheral
devices and companion chips do not directly supply addresses and commands to the memory
system. Instead, the addresses and commands are maintained in 32 DMA channels within the
DMA controller. Every DMA request from the peripheral device and companion chip generates a
memory bus cycle. The DMA controller of the PXA27x processor supports both flow-through and
fly-by transfers.
5.2

Signals

See Table 5-1
Table 5-1. DMA Interface Signals
Signal Name
DREQ<2:0>
DVAL<1:0>
®
Intel PXA27x Processor Family Design Guide
for the list of signals used to interface to the DMA controller.
Type
External Companion Chip Request
The DMA controller detects the positive edge of the DREQ
signal to log a request. The external companion chip
asserts the DREQ signal when a DMA transfer request is
required. The signal must remain asserted for four
MEM_CLK cycles to allow the DMA controller to recognize
the low-to-high transition. When the signal is de-asserted,
the signal must remain de-asserted for at least four
MEM_CLK cycles. The DMA controller registers the
transition from low to high to identify a new request.
Input
The external companion chip need not wait until the
completion of the data transfer before asserting the next
request. This companion chip has up to 31 outstanding
requests on each of the DREQ<2:0> pins. The number of
pending requests are logged in special status registers,
DRQSRx.
Requests on pins DREQ<1:0> are used for data transfers
in either fly-by or flow-through modes.
Requests on pins DREQ<2> are used for data transfers in
flow-through mode only.
External Companion Chip Valid
Output
The memory controller asserts DVAL to notify the
companion chip. Either data must be driven or is valid.
Description
5
®
PXA27x
II:5-1