Table 63. Bclk/Bclk#[1:0] Routing Guidelines - Intel 855PM Design Manual

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Table 63. BCLK/BCLK#[1:0] Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
BCLK Skew Between Agents
Differential Pair Spacing
Trace Width
Spacing to Other Traces
System Board Impedance – Differential
System Board Impedance – Odd Mode
Processor Routing Length – L1, L1': Clock Driver
to Rs
Processor Routing Length – L2, L2': Rs to Rt
Node
Processor Routing Length – L3, L3': Rt Node to
Rt
Processor Routing Length – L4, L4': Rt Node to
Receiver
MCH Routing Length – L1, L1': Clock Driver to Rs Max = 0.50 inches
MCH Routing Length – L2, L2': Rs to Rt Node
MCH Routing Length – L3, L3': Rt Node to Rt
MCH Routing Length – L4, L4': Rt Node to
Receiver
Processor L1/L1' and MCH L1/L1' Length
Matching
Clock Driver-to-Processor and Clock Driver-to-
MCH Length Matching (L1 + L2 + L4)
Processor BCLK (L1 + L2 + L4) and BCLK# (L1'
+ L2' + L4') Length Matching
MCH BCLK (L1 + L2 + L4) and BCLK# (L1' + L2'
+ L4') Length Matching
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
NOTES:
®
Intel 855PM Chipset Platform Design Guide
Parameter
Platform Clock Routing Guidelines
Routing Guidelines
HOST_CLK
Source Shunt Termination
Ground Referenced (Contiguous over entire
length)
500 ps Total Budget: 250 ps for Flight Skew;
100 ps for Pin-to-Pin Skew; 150 ps for Jitter
7 mils
4 mils
Min = 25 mils
100 ± 15%
50 ± 15%
Max = 0.50 inches
Min = 0 inches
Max = 0.20 inches
Min = 0 inches
Max = 0.50 inches
Min = 2.0 inches
Max = 8.0 inches
Min = 0 inches
Max = 0.20 inches
Min = 0 inches
Max = 0.50 inches
Min = 2.0 inches
Max = 8.0 inches
± 10 mils
- 400 mils ± 50 mils
± 10 mils
± 10 mils
33 ± 5%
49.9 ± 1% (for 55 MB impedance)
Figure Notes
1
Figure 130 2, 3, 4, 5
6, 7
8
9
10
Figure 129 14
Figure 129 14
Figure 129 14
Figure 129
Figure 129 14
Figure 129 14
Figure 129 14
Figure 129
16
11
Figure 129 12
Figure 129 13
233