Intel 855PM Design Manual page 12

Figure 47. Intel® Pentium® M Processor / Intel® Celeron® M Processor VID[5:0] Escape
Routing Layout Example .......................................................................................... 95
Figure 48. Power On Sequencing Timing Diagram ................................................................. 97
Figure 49. V
Figure 50. V
Figure 51. Voltage Regulator Multi-Phase Topology Example.............................................. 100
Figure 52. Buck Voltage Regulator Example......................................................................... 101
Figure 53. High Current Path With Top MOSFET Turned ON .............................................. 101
Figure 54. High Current Path During Abrupt Load Current Changes.................................... 102
Figure 55. High Current Path with Top and Bottom MOSFETs Turned Off (Dead Time) ..... 102
Figure 56. High Current Path With Bottom MOSFET(s) Turned ON ..................................... 103
Figure 57. Estimated Processor Current Consumption Change During STPCLK Exit ......... 105
Figure 58. Intel Pentium M Processor and Intel Celeron M ProcessorSocket Core Power
Delivery Corridor..................................................................................................... 107
Figure 59. Processor Core Power Delivery and Decoupling Concept................................... 108
Figure 60. V
(Primary and Secondary Side Layers) ................................................................... 112
Figure 61. Processor Core Power Delivery "North Corridor" Zoom In View.......................... 112
Figure 62. V
Figure 63. Recommended SP Cap Via Connection Layout (Secondary Side Layer) ........... 113
Figure 64. Processor V
Figure 65. Processor V
Figure 66. Intel 855PM MCH V
Figure 67. Intel 855PM MCH V
Example.................................................................................................................. 118
Figure 68. Intel 855PM MCH V
Figure 69. V
Figure 70. V
Figure 71. V
Figure 72. Data Signal Routing Topology .............................................................................. 127
Figure 73. DQ/CB to DQS Trace Length Matching Requirements ........................................ 130
Figure 74. SDQS to SCK/SCK# Trace Length Matching Requirements ............................... 132
Figure 75. Data Signals Group Routing Example.................................................................. 133
Figure 76. Control Signal Routing Topology.......................................................................... 135
Figure 77. Control Signal to SCK/SCK# Trace Length Matching Requirements................... 137
Figure 78. Control Signals Group Routing Example.............................................................. 138
Figure 79. Command Signal Routing for Topology 1............................................................. 139
Figure 80. Command Signal to SCK/SCK# Trace Length Matching Requirements.............. 142
Figure 81. Command Signals Topology 1 Routing Example................................................. 143
Figure 82. Command Signal Routing for Topology 2............................................................. 144
Figure 83. Command Signal to SCK/SCK# Trace Length Matching Requirements.............. 147
Figure 84. Command Signals Topology 2 Routing Example................................................. 148
Figure 85. DDR Clock Routing Topology (SCK/SCK#[5:0]) .................................................. 149
Figure 86. SCK/SCK# Trace Length Matching Requirements .............................................. 152
Figure 87. Clock Pair Trace Length Matching Requirements
Figure 88. Clock Signal Routing Example ............................................................................. 154
Figure 89. DDR Feedback (RCVEN#) Routing Topology...................................................... 155
Figure 90. RCVEN# Signal Routing Example........................................................................ 157
Figure 91. Data Signal Group (SDQ[71:0], SDQS[8:0]) Routing Topology -
PC2700, PC2100 and PC1600 Compliant ............................................................. 158
Figure 92. DDR Memory Thermal Sensor Placement ........................................................... 165
Figure 93. AGP Layout Guidelines ........................................................................................ 171
Figure 94. Hub Interface Routing Example............................................................................ 177
Figure 95. Hub Interface with Single Reference Voltage Divider Circuit ............................... 180
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Block Diagram ................................................................................................ 98
CCP
Block Diagram............................................................................................ 98
CC-MCH
Power Delivery and Decoupling Example -
CC-CORE
Power Delivery and Decoupling Example (Layers 3, 5, and 6) ............. 113
CC-CORE
Power Delivery and Decoupling Concept ................................... 116
CCP
Power Plane and Decoupling Example ...................................... 117
CCP
Power Plane and Decoupling Concept........................... 118
CCP
Power Plane and Decoupling Recommended Layout
CCP
Power Delivery Recommended Layout (Zoom In View). 119
CCP
Power Delivery and Decoupling Concept ................................................ 121
CC-MCH
Power Planes and Decoupling Example ................................................. 122
CC-MCH
Secondary Layer Decoupling Capacitor Placement (Zoom in View) ...... 123
CC-MCH
............................................... 153
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Intel 855PM Chipset Platform Design Guide
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