Ich4-M Power Management Interface - Intel 855PM Design Manual

Platform Design Checklist
14.8.6.

ICH4-M Power Management Interface

Pin Name
DPRSLPVR
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
BATLOW#
CLKRUN#
PWRBTN#
PWROK
RI#
RSMRST#
THRM#
312
ICH4-M Power Management Interface – Resistor Recommendations
System
Pull up/ Pull
down
See Notes 10 k
Pull up to 10 k
Vcc3_3
Pull down to 100 k
GND
See Notes
Pull up to 10 k
V3ALWAYS
Pull down to 100 k
GND
Pull up to 8.2 k
Vcc3_3
(If NOT
(If NOT USED)
Used)
Series
Damping
External pull down not required. Signal has
integrated pull down in ICH4-M.
External pull up not required. Signals driven by
ICH4-M.
Pull up is not required if it is used. However,
signal must not float if it is NOT being used
(Signal should be pull up to V3ALWAYS
through a 10 k pull up resistor).
When asserted, this ICH4-M input signal will
indicate a system request to go into a sleep
event or cause a wake event (if the system is
already in a Sleep state).
This signal is recommended to connect to a
power button or any other equivalent driver.
This signal has integrated pull up External pull
up/down not required.
RTC well input requires pull down to reduce
leakage from coin cell battery in G3. Input must
not float in G3.
This signal should be connected to power
monitoring logic and should go high no sooner
than 10 ms after both Vcc3_3 and Vcc1_8 have
reached their nominal voltages.
Intel CRB uses a 100 k pull down to reduce
leakage from coin cell battery in G3.
If this signal is enabled as a wake event, it is
important to keep this signal powered during a
power loss event. If this signal goes low
(active), when power returns the RI_STS bit will
be set and the system will interpret that as a
wake event.
RSMRST# is a RTC well input and requires pull
down to reduce leakage from coin cell battery in
G3. Input must not float in G3.
This signal should be connected to power
monitoring logic and should go high no sooner
than 5 ms after both VccSus3_3 and
VccSus1_5 have reached their nominal
voltages.
Intel CRB uses a 100 k pull-down to reduce
leakage from coin cell battery in G3.
If THRM# Is Used:
THRM# is a 3.3 V tolerant signal. Voltage
translation may be required if other thermal
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Intel 855PM Chipset Platform Design Guide
R
Notes