Intel 855PM Design Manual page 115

Platform Power Requirements
R
Placement and layout of the ten, 0.1-µF capacitors should be strictly adhered to in order to minimize the
effective loop inductance of these capacitors. All the capacitors should be placed within 45 mils (center-
to-center) of the V pin rows. Ground vias for the 0.1-µF capacitors should also be placed within 45
CCP
mils of the capacitor pads and shorted with a 25-mil wide trace to the ground via.
In Figure 65, the secondary side shows one of the 150- F POSCAPs being placed next to the processor
socket close to the DATA pins. Notice that the ground pin connection of the POSCAP is extended
towards the V pad of the capacitor with two ground vias placed under the body of the POSCAP. This
CCP
is done in order to minimize the inductance of the POSCAP connection by minimizing the loop area of
current flow.
Figure 65 also shows that a connection on the secondary side to the Legacy side V pins of the
CCP
processor pin-map is not possible because it is blocked by the secondary side V flood that
CC-CORE
connects the south side 0805 capacitors with the twenty-four V pins on the south side of the
CC-CORE
processor pin-map (see secondary side of Figure 60 in Section 5.9.3). Thus, the primary side of Figure
65 illustrates a V flood shape that shorts the DATA, ADDR, and Legacy V pins of the processor
CCP CCP
pin-map. The very specific arrangement of the V /GND vias illustrated on the primary side of Figure
CCP
65 should be strictly followed to guarantee that each V BGA ball of the processor pin-map connects
CCP
to the V shape flood on the primary side. To guarantee robust connection to the ground balls around
CCP
the V pins, 25-mil wide dog bones should be used while the V BGA balls of the processor socket
CCP CCP
are advised to use the wide V flood in between the Vss dog bones as illustrated on the primary side of
CCP
Figure 65.
A V flood "channel" should pass through the processor pin field on the bottom right side of the
CCP
processor socket to continue the V feed to the ITP700FLEX debug port. A V flood "channel" to
CCP CCP
the ICH4-M is provided from the main V flood plane of the MCH and circumvents the 1.5-V and
CCP
1.8-V plane floods to the MCH by routing around the AGP bus signal quadrant (not shown in figures).
Refer to Figure 65 for more details.
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Intel 855PM Chipset Platform Design Guide