Ddr System Memory Interface Strapping; Ecc Disable Guidelines; Intel 855Pm Mch Ecc Functionality Disable - Intel 855PM Design Manual

Chipset platform for use with pentium m and celeron m processors
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R
Data Signal Name
SCAS#
SWE#
SCKE[0]
SCKE[1]
SCS#[0]
SCS#[1]
RCVENOUT#
6.3.

DDR System Memory Interface Strapping

The Intel 855PM MCH has pins that require termination for proper component operation.
For the MCH, the ST[0] pin does not require any strapping for normal operation. This signal has an
internal pull-up that straps the MCH for DDR memory during reset. However, a stuffing option for a 1-
k ± 5% pull-up to a 1.5-V source can be provided for testing purposes.
6.4.

ECC Disable Guidelines

The Intel 855PM MCH can be configured to operate in an ECC data integrity mode that allows for
multiple bit error detection and single bit error correction. This option to design for and support ECC
DDR memory modules is dependent on design objectives. By default, ECC functionality is disabled on
the platform. For designs that support ECC memory, see Sections 6.1.1 and 6.1.4 for details on signal
topologies and routing guidelines.
6.4.1.

Intel 855PM MCH ECC Functionality Disable

If non-ECC memory modules are to be the only supported memory type on the platform, then the eight
DDR check bits signals, associated strobe, and differential clock pairs associated with the ECC device
for each SO-DIMM can be left as no connects on the Intel 855PM MCH. This includes SDQ[71:64],
SDQS8, and the two differential clock pairs that are not routed to the SO-DIMMs. The following
discussion mentions details for the MCH system memory registers.
The DRAM Data Integrity Mode (DDIM) bit of the DRC register (Device 0; Offset 7C-7Fh; bit 21)
provides the option to enable or disable ECC operation mode in the MCH. By default, this bit is set to
'0' and ECC functionality is disabled. In such a case, the SDQ[71:64] and SDQS eight pins of the MCH
can be left as no connects.
®
Intel
855PM Chipset Platform Design Guide
Intel 855PM MCH Package
Trace Length (mils)
COMMAND – Misc
491
401
CONTROL – SCKE
557
600
CONTROL – SCS#
516
539
RECEIVE ENABLE
661
System Memory Design Guidelines (DDR-SDRAM)
Intel 855PM MCH Package
Data Signal Name
Trace Length (mils)
SRAS#
SCKE[2]
SCKE[3]
SCS#[2]
SCS#[3]
RCVENIN#
447
506
573
516
610
348
161

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