Mechanical Considerations; Electrical Considerations; Intel Pentium M Processor / Intel Celeron M Processor And Intel 855Pm Mch Fsb Signal Package Lengths - Intel 855PM Design Manual

FSB Design Guidelines
4.3.3.1.

Mechanical Considerations

The LAI is installed between the processor socket and the Intel Pentium M/Intel Celeron M processor.
The LAI pins plug into the socket, while the processor in the 478-pin package plugs into a socket on the
LAI. Cabling this part of the LAI egresses the system to allow an electrical connection between the
processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keep-out
volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.
System designers must make sure that the keepout volume remains unobstructed inside the system. Note
that it is possible that the keepout volume reserved for the LAI may include space normally occupied by
the processor heat sink. If this is the case, the logic analyzer vendor will provide a cooling solution as
part of the LAI.
4.3.3.2.

Electrical Considerations

The LAI will also affect the electrical performance of the FSB. Therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that their tool will work in the system. Contact the logic analyzer vendor for electrical
specifications as load models for the LAI solution they provide.
4.4. Intel Pentium M Processor / Intel Celeron M Processor
and Intel 855PM MCH FSB Signal Package Lengths
Table 18 lists the package trace lengths of the Intel Pentium M processor / Intel Celeron M processor
and the Intel 855PM MCH for the source synchronous data and address signals. All the signals within
the same group are routed to the same length as listed below with ± 0.1-mil accuracy. As a result of this
package trace length matching, no motherboard trace length compensation is needed for these signals.
Refer to Section 4.1.3 for further details. The processor and MCH package traces are routed as micro-
strip lines with a nominal characteristic impedance of 55
88
± 15%.
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Intel 855PM Chipset Platform Design Guide
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