Topology 1C: Open Drain (Od) Signals Driven By The Processor - Prochot; Figure 18. Routing Illustration For Topology 1C; Table 10. Layout Recommendations For Topology 1C - Intel 855PM Design Manual

FSB Design Guidelines
4.1.4.1.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor – PROCHOT#
The Topology 1C OD signal PROCHOT#, should adhere to the following routing and layout
recommendations. Table 10 lists the recommended routing requirements for the PROCHOT# signal of
the processor. The routing guidelines allows the signal to be routed as either a micro-strip or strip-line
using 55
for providing voltage translation between the processor's PROCHOT# signal and a system receiver that
utilizes a 3.3-V interface voltage (shown as V_IO_RCVR).
Series resistor Rs is a component of the voltage translation logic and serves as a driver isolation resistor.
Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to emphasize
the placement of Rs with respect to Q1. The placement of Rs a distance L3 before the Q1 BJT is a
specific implementation of the generalized voltage translator circuit shown in Figure 24. Rs should be
placed at the beginning of the T-split from the PROCHOT# signal. The pull-up voltage for termination
resistor Rtt is V
Intel recommends that PROCHOT# be routed using the voltage translation logic shown in Figure 18.
The receiver at the output of the voltage translation circuit can be any system receiver that can function
properly with the PROCHOT# signal given the nature and usage model of this pin. PROCHOT# is
capable of toggling hundreds of times per second to signal a hot temperature condition.

Figure 18. Routing Illustration for Topology 1C

Table 10. Layout Recommendations for Topology 1C

L1
0.5" – 12.0" 0" – 3.0" 0" – 3.0" 0.5" – 12.0" 330
0.5" – 12.0" 0" – 3.0" 0" – 3.0" 0.5" – 12.0" 330
54
± 15% characteristic trace impedance. Figure 18 shows the recommended implementation
(1.05 V).
CCP
Intel
Pentium M
Processor
VCCP
Rtt
L2
L1
Rs
L2 L3 L4
3.3V
3.3V
R1
Q2
Q1
L3
3904
Rs R1 R2-
± 5% 1.3 k ± 5% 330
± 5% 1.3 k ± 5% 330
®
Intel 855PM Chipset Platform Design Guide
System Receiver
V_IO_RCVR
R2
L4
3904
Transmission
Rtt
Line Type
± 5% 56 ± 5% Micro-strip
± 5% 56 ± 5% Strip-line
R