Figure 36. Intel 855Pm Mch Hrcomp[1:0] Resistor Layout; Figure 37. Intel 855Pm Mch Hswng[1:0] Reference Voltage Generation Circuit - Intel 855PM Design Manual

FSB Design Guidelines

Figure 36. Intel 855PM MCH HRCOMP[1:0] Resistor Layout

The MCH's AGTL+ I/O buffer resistive compensation mechanism also requires the generation of
reference voltages to the HSWNG[1:0] pins with a value of 1/3* V
HSWNG[1:0] voltage generation is illustrated in Figure 37. Two resistive dividers with R1a = R1b =
301 ± 1% and R2a = R2b = 150
act as decoupling capacitors and connect HSWNG[1:0] to V
within 0.5 inches of their respective pins and connected with a 15-mil wide trace. To avoid coupling
with any other signals, maintain a minimum of 25 mils of separation to other signals.

Figure 37. Intel 855PM MCH HSWNG[1:0] Reference Voltage Generation Circuit

Figure 38 illustrates recommended layout for the HSWNG[1:0] components that are placed on the
secondary side to minimize their interconnect length and space they occupy. In the example, C1a and
C1b are placed closer to HSWNG pins than R1a, R1b, R2a, and R2b. It is important to keep only the
connection of C1a and C1b to the HSWNG[1:0] with a 15-mil wide trace. The R1a (R1b) to R2a (R2b)
connection can be done with a narrow trace as well as the connection to the pin that in the layout
72
SECONDARY SIDE
± 1% generate the HSWNG[1:0] voltages. C1a = C1b = 0.01 µF
+VCCP
R1a
301Ω
C1a
1%
0.1uF
HSWNG[0]
HSWNG[0]
R2a
150Ω
1%
AD12
Pin
GND
Via
. The schematics for
CCP
. HSWNG components should be placed
CCP
HSWNG[1]
Intel
HSWNG[1]
855PM
MCH
®
Intel 855PM Chipset Platform Design Guide
R
AE1
Pin
GND
Via
HRCOMP[0]
HRCOMP[1]
+VCCP
R1b
C1b 301
0.1 uF 1%
R2b
150
1%