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Table 18.
HOST_CLK Routing Guidelines
Signal Group
Reference Plane
Layer Assignment
Characteristic Trace Impedance (Zo)
Trace Width – W
Spacing within HOST_CLK pairs – S
HOST_CLK to Signal Spacing – S1
Serpentine Spacing
Routing Length – L1, L1': Clock Driver to Rs
Routing Length – L2, L2': Rs to Rs-Rt Node
Routing Length – L3, L3': Rs-Rt Node to Rt
Routing Length – L4, L4'
Host_CLKn to Host_CLKp Length Matching
Rs Series Termination Value
Rt Shunt Termination Value
Notes:
1.
These traces must not cross any plane splits on adjacent layers. In addition, these must not switch
layers for the L4 segment in
2.
Routing guidelines are recommended for both 3 and 8 layer.
3.
Clock traces are routed in a differential configuration. Maintain the minimum recommended spacing
between the two traces of the pair. Maintain uniform spacing along the entire length of the trace. Do
not exceed the maximum trace spacing, as this will degrade the noise rejection of the network.
Figure 54.
Trace Spacing for HOST_CLK Clocks
8.2.1.2
Host_CLK General Routing Guidelines
The host bus clocks delivered to the processor can be either microstrip or stripline
routing but must be ground referenced to minimize dielectric and impedance
variations. Do not split up the two halves of a differential clock pair between layers.
Route clocks to agents on the same physical routing layer. See
requirements.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
95
®
Intel
EP80579 Integrated Processor Product Line—Platform System Clock
Parameter
1
Figure
53.
W
HOST_
CLK
S1
h
Ground Plane
Routing Guidelines
Host_CLK:
• EP80579 (CLKP100/CLKN100)
• ITP Debug Port (BCLKP/BCLKN)
Ground Referenced, Microstrip or stripline
Layers 3 or 8
100 Ω ±10% (differential)
microstrip: 4.5 mils
stripline: 4.75 mils
10 mils
20 mils
20 mils
0.5 in. max (Differential)
0.2 in. max (Differential)
0.2 in. max (Differential)
Min:1 in.
Max: 10 in.
±5 mils
33 Ω ±5%
49.9 Ω ±1%
W
HOST_
CLK
S
Order Number: 320068-005US
Figure
Figure 54
Figure 54
Figure 54
Figure 54
Figure 53
Figure 53
Figure 53
Figure 53
Figure 53
Figure 53
S1
Table 18
for detailed
May 2010
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