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A
7,9,15,17,20,24,27,29,32,34,40,41
14
U17A
1
38
ON_BOARD_VR_PWRGD
74HC00
4
INTERPOSER_PRES#
2
7
7,9,15,17,20,24,27,29,32,34,40,41
+V3.3
14
U17C
U17D
14
10
PWRGD3
74HC00
8
13
74HC00
9
12
7
R363
7
100K
OFF_BOARD_VR_PWRGD
3
Processor VID TABLE
VID
VCC
VID
Core
4
3
2
1
0
5
4
3
2
1
0
0
0
0
0
0
1.708
1
0 0
0
0
0
0
0
0
1
1.692
1
0 0
0
0
0
0
0
1
0
1.676
1
0 0
0
0
0
0
0
1
1
1.660
1
0 0
0
0
0
0
1
0
0
1.644
1
0 0
1
0
0
0
1
0
1
1.628
1
0 0
1
0
0
0
1
1
0
1.612
1
0 0
1
2
0
0
0
1
1
1
1.596
1
0 0
1
0
0
1
0
0
0
1.580
1
0 1
0
0
0
1
0
0
1
1.564
1
0 1
0
0
0
1
0
1
0
1.548
1
0 1
0
0
0
1
0
1
1
1.532
1
0 1
0
0
0
1
1
0
0
1.516
1
0 1
1
0
0
1
1
0
1
1.500
1
0 1
1
0
0
1
1
1
0
1.484
1
0 1
1
0
0
1
1
1
1
1.468
1
0 1
1
0
1
0
0
0
0
1.452
1
1 0
0
0
1
0
0
0
1
1.436
1
1 0
0
0
1
0
0
1
0
1.420
1
1 0
0
0
1
0
0
1
1
1.404
1
1 0
0
0
1
0
1
0
0
1.388
1
1 0
1
0
1
0
1
0
1
1.372
1
1 0
1
0
1
0
1
1
0
1.356
1
1 0
1
0
1
0
1
1
1
1.340
1
1 0
1
1
0
1
1
0
0
0
1.324
1
1 1
0
0
1
1
0
0
1
1.308
1
1 1
0
0
1
1
0
1
0
1.292
1
1 1
0
0
1
1
0
1
1
1.276
1
1 1
0
0
1
1
1
0
0
1.260
1
1 1
1
0
1
1
1
0
1
1.244
1
1 1
1
0
1
1
1
1
0
1.228
1
1 1
1
0
1
1
1
1
1
1.212
1
1 1
1
A
B
VR PWRGD CIRCUIT
+V3.3
14
U17B
PWRGD1
3
4
74HC00
6
IMVP_PWRGD 34
5
7
PWRGD2
11
R269
10K
2
Q36
C288
1
34
IMVP_PWRGD
BSS84
1uF
20%
VCC
Core
0
3
0
0
1.196
0
1
1.180
1
0
1.164
1
1
1.148
0
0
1.132
0
1
1.116
+V3.3S 5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
1
0
1.100
1
1
1.084
0
0
1.068
0
1
1.052
1
0
1.036
1
1
1.020
0
0
1.004
1
37
CORE_VR_ON
0
1
0.988
2
1
0
0.972
29
VR_SHUT_DOWN#
1
1
0.956
0
0
0.940
0
1
0.924
1
0
0.908
1
1
0.892
0
0
0.876
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
0
1
0.860
1
0
0.844
U43_TP1
1
1
0.828
U43_TP2
0
0
0.812
0
1
0.796
R3007
R3008
1
0
0.780
1K
1K
1
1
0.764
0
0
0.748
0
1
0.732
1
0
0.716
1
1
0.700
B
C
+V3.3ALWAYS
U4
1
41
PWR_PWROK
2
17
V1.5_PWRGD
74AHC1G08
5,9,16,17,18,19,20,24,25,26,29,33,34,41
+V3.3ALWAYS
U8
1
40
DDR_VR_PWRGD
2
18
V5A_PWRGD
74AHC1G08
+V3.3S
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
+V3.3S
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
R250
1.58K
1%
10
VDD+
OPAMP_N
U43A
2
-
VR_PWRGD_ICH_D
1
TLV2463
OPAMP_EN
5
OPAMP_P
3
+
GND
4
R251
2K_1%
+V3.3S 5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
+V5S
9,17,20,21,24,31,32,33,35,37,38,41,42
U18
J30
OFF_BOARD_VR_PWRGD
1
2
OFF_BOARD_VR_ON
4
3
4
NC5_D
5
6
7
8
74AHC1G08
9
10
11
12
13
14
15
16
17
18
Connector 1
19
20
21
22
(rows A,B)
+V3.3S
23
24
25
26
10
VDD+
U43B
27
28
TLV2463
29
30
8
31
32
-
33
34
9
35
36
6
37
38
7
39
40
+
20x2_Header
GND
4
VR Interposer Headers
C
D
5,9,16,17,18,19,20,24,25,26,29,33,34,41
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
U9
MAIN_PWROK
4
1
4
PM_PWROK
74AHC1G08
2
4
34
IMVP_PWRGD
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
R268
10K
INTERPOSER_PRES#
OFF_BOARD_VR_ON
+V3.3S
5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
R256
10K
CR23
3
1
VR_PWRGD_ICH 16,34
BAT54
38,42
VR_VID0
38,42
VR_VID1
38,42
VR_VID2
INTERPOSER_PRES#
PM_STPCPU# 14,16,34,38
PM_DPRSLPVR 16,34,38
TP_NC_5 3
R52
0
+VDC 18,37,38,41
Title
Processor Voltage Regulator Module
Size
Project:
Custom
855PM Platform
Date:
Monday, February 24, 2003
D
E
+V3.3S
16,18,22,29,34
R255
10K
VR_PWRGD_CK408# 14
3
R254
IMVP_PWRGD_D
Q38
1
2N3904
2
10K_1%
+V3.3S
R366
1M
U19
1
4
ON_BOARD_VR_ON 38
2
74AHC1G08
+V3.3S 5,9,10,14,15,17,18,20,23,28,30,31,32,33,37,38,41,42
+V5S
9,17,20,21,24,31,32,33,35,37,38,41,42
J29
1
2
VR_VID3 38,42
3
4
VR_VID4 38,42
5
6
VR_VID5 38,42
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Connector 2
21
22
(rows C,D)
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20x2_Header
Document Number
Rev
Sheet
36
of
47
E
4
3
2
1
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