Intel 855PM Design Manual page 297

R
DU[4:1]
GND[1:0]
RESET(DU)
VDDID
SA[2:0]
Connect to VCC3_3
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Intel 855PM Chipset Platform Design Guide
See Notes
See Notes
See Notes
See Notes
DDR SO-DIMM Interface—Misc Signal
Tie to GND /
See Notes
Platform Design Checklist
This signal can be left as NC (No Connect).
This signal can be left as NC (No Connect).
This signal can be left as NC (No Connect).
This signal can be left as NC (No Connect).
SPD EEPROM Address Detection:
For 1st SO-DIMM address 'A0':
SA[2:0] should be tied to GND
For 2nd SO-DIMM address 'A2':
SA[0] – Tie to VCC3_3
SA[2:1] – Tie to GND
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