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Platform Power Requirements
5.9.4.
Intel Pentium M Processor / Intel Celeron M Processor and
Intel 855PM MCH V
The 400-MHz high frequency operation of the Intel Pentium M/Intel Celeron M and Intel 855PM
MCH's FSB requires careful attention to the design of the power delivery for V
processor and MCH. Table 21 summarizes the V
150-µF POSCAPs with an ESR of 36 m (typ) should be used for bulk decoupling. One capacitor
should be placed next to the processor socket and one capacitor in close proximity to the MCH package.
The current layout example recommends the placement of each POSCAP on the secondary side of the
motherboard to minimize inductance. In addition, ten 0.1-µF X7R capacitors in a 0603 form factor
should be placed on the secondary side of the motherboard under the processor socket cavity next to the
V
pins of the processor. Five capacitors should be spread out near the Data signal side and five
CCP
capacitors near the Address signal side of the processor socket's pin-map. Eight more 0.1-µF X7R
capacitors in a 0603 form factor should be placed on the secondary side of the motherboard next to the
V
pins of the MCH. The processor and MCH V
CCP
preferably on the secondary side such that it will extend across the whole "shadow" of the FSB signals
routed between the processor and MCH. The 1.05-V, VR feed point into the V
roughly in between the processor and MCH.
Table 21. V
Decoupling Guidelines
CCP
Low Frequency Decoupling (Polymer Covered Tantalum –
POSCAP, Neocap, KO Cap)
High Frequency Decoupling (0603 MLCC, >= X7R) Place
next to the processor
High Frequency Decoupling (0603 MLCC, >= X7R) Place
next to the Intel 855PM MCH
NOTES:
Place one capacitor close to processor and one capacitor close to the Intel 855PM MCH.
1.
5.9.4.1.
Processor V
Figure 64 illustrates a conceptual cross sectional view of the recommended processor V
delivery layout. Due to the presence of the Layer 7 GND plane that is 4 mils above Layer 8 (see Figure
2), the secondary side layer (Layer 8) V
factor 0.1-µF capacitors and the 150-µF, POSCAP capacitor. At the same time, the V
secondary side efficiently connects the capacitors to the processor V
are placed on the secondary side under the socket cavity shadow while the 150- F, POSCAP capacitor
is placed to the processor socket shadow close to the DATA side pins of the secondary side. Figure 65
shows a conceptual cross sectional view (left side of Figure 65) of the V
translates into an actual layout on the primary and secondary sides of the motherboard as shown on the
right side of Figure 65. The secondary side of Figure 65 utilizes a wide V
MCH that shorts the V
0603 form factor 0.1-µF decoupling capacitors that are placed on the secondary side in the shadow of
the processor socket cavity. These capacitors provide decoupling for the V
114
Voltage Plane and Decoupling
CCP
Description
Voltage Plane and Decoupling
CCP
plane creates a low inductance short between the 0603 form
CCP
pins of the DATA and ADDR side of the processor pin-map with the ten,
CCP
(1.05 V) voltage rail decoupling requirements. Two
CCP
pins should be shorted with a wide, V
CCP
Cap (µF)
ESR
(m
µ
36 m
2 x 150
F
(typ) / 2
µ
16 m
10 x 0.1
F
(typ) / 10
µ
16 m
8 x 0.1
F
(typ) / 8
pin vias. Ten, 0603 capacitors
CCP
CCP
CCP
CCP
®
Intel
855PM Chipset Platform Design Guide
R
(1.05 V) to the
CCP
plane
CCP
plane should be
CCP
ESL (nH)
Notes
2.5 nH / 2
1
0.6 nH / 10
0.6 nH / 8
power
CCP
plane on the
CCP
power delivery and how it
plane coming from the
pins of the processor.
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