Decoupling Recommendations (Mch); Memory Decoupling Recommendation - Intel 855PM Design Manual

R
14.6.4.

Decoupling Recommendations (MCH)

Pin Name
SMRCOMP Tie to Vcc1_25[DDR_Vtt]
Vcc1_8
VccSus2_5
VCC-MCH
VCCGA, VCCHA
VCCP
14.6.5.

Memory Decoupling Recommendation

Pin Name
Vcc1_25[DDR_Vtt]
VccSus2_5
®
Intel 855PM Chipset Platform Design Guide
MCH– Decoupling Recommendations
Configuration F
0.1 µF
Tie to Vcc1_8 0.1 µF
Tie to VccSus2_5 0.1 µF
Tie to VCC_MCH 150 µF
2.2 µF
220 nF
47 nF
22 nF
15 nF
10 nF
Tie to Vcc1_8 10 µF
10 nF
Tie to VCCP 10 µF
0.1 µF
Memory Decoupling Recommendations
Configuration F
See Notes 0.1 µF
0.1 µF
1
Qty
1 Decoupling capacitor must be connected to
the power-side of the RCOMP resistor.
2 Two 0.1 µF capacitors are recommended
for Vcc1_8 decoupling. All values are
preliminary.
See Section 8.5 for details
15 Place within 150 mils of MCH package.
See Section 11.5.1.1
2 See Section 5.9.5for details.
1
1
1
1
1
1
1 VCCGA and VCCHA can both share a 10
µF and 10nF decoupling capacitor.
1
Polymer covered tantalum. Place next to
1
the MCH.
8
0603 MLCC, >= X7R. Place next to the
MCH.
1
Qty
See Notes In S3, Vcc1_25[DDR_Vtt] (DDR channel
termination voltage) can be turned OFF.
Place one 0.1 µF close to every 2 pull up
resistors terminated to Vcc1_25[DDR_Vtt].
See Section 11.7.4 for details.
9 Place capacitors between the SO-DIMMs .
See Section 11.5.1.2 for details.
Platform Design Checklist
Notes
Notes
301