Figure 2. Recommended Board Stack-Up Dimensions - Intel 855PM Design Manual

General Design Considerations
To ensure impedance control of 55 , the primary and secondary side layer micro-strip lines should
reference solid ground planes on Layer 2 and Layer 7, respectively.

Figure 2. Recommended Board Stack-Up Dimensions

Internal signal traces on Layer 3 and Layer 6 are unbalanced strip-lines. To meet the nominal 55-
characteristic impedance for these traces, they reference a solid ground plane on Layer 2 and Layer 7.
Since the coupling to Layer 4 and Layer 5 is still significant, (especially true when thinner stack-ups use
balanced strip-lines on internal layers) these layers are converted to ground floods in the areas of the
motherboard where the high-speed interfaces like the FSB or DDR system memory are routed. In the
remaining sections of the motherboard layout the Layer 4 and Layer 5 layers are used for power
delivery.
For 55- characteristic impedance Layer 3 (Layer 6), strip-lines have a 4-mil final trace width and are
separated by a core dielectric thickness of 4 mils after lamination from the Layer 2 (Layer 7) ground
plane and 11-mil thickness prepreg after lamination to separate it from Layer 4 (Layer 5). The starting
thickness of these core and prepreg dielectric layers before lamination is 5 mils and 12 mils,
respectively.
The secondary side layer is also used for power delivery in many cases since it benefits from the thick
copper plating of the external layer plating as well as referencing the close (4-mil prepreg thickness)
Layer 7 ground plane. The benefit of such a stack-up is low inductance power delivery.
OEMs may choose to use different stack-ups (number of layers, thickness, trace width, etc.) from the
one example outlined in Figure 2. However, the following key elements should be observed:
1. Final post lamination, post etching, and post plating dimensions should be used for electrical
model extractions.
2. Power plane layers should be 1 oz thick and signal layers should be ½ oz thick.
3. External layers become 1 – 1.5 oz (1.2 – 2 mils) thick after plating
30
Final Dimensions after Final Dimensions after
Er=4.3 Er=4.3
Lamination, Etching, Plating Lamination, Etching, Plating
1.5mil 1.5mil
L1 Signals L1 Signals After After
plating plating
L2 GND Plane L2 GND Plane L2 GND Plane
L3 Signals L3 Signals L3 Signals
0.6mil 0.6mil
Prepreg 11.0mil Prepreg 11.0mil
L4 GND/PWR L4 GND/PWR L4 GND/PWR
Plane Plane Plane
L5 GND/PWR L5 GND/PWR L5 GND/PWR
Plane Plane Plane
Prepreg 11.0mil Prepreg 11.0mil
0.6mil 0.6mil
L6 Signals L6 Signals L6 Signals
L7 GND Plane L7 GND Plane L7 GND Plane
L8 Signals/ L8 Signals/
Power Power
1.0mil 1.0mil
Solder Mask Solder Mask
5.0mil 5.0mil
1.2mil 1.2mil
Prepreg 4.0mil Prepreg 4.0mil
Core 4.0mil Core 4.0mil
4.0mil 4.0mil
1.2mil 1.2mil
Core 12.0mil Core 12.0mil
1.2mil 1.2mil
4.0mil 4.0mil
1.2mil 1.2mil
Core 4mil Core 4mil
Prepreg 4.0mil Prepreg 4.0mil
1.5mil 1.5mil
After plating After plating
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Intel 855PM Chipset Platform Design Guide
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