14.8.11. Lan Interface - Intel 855PM Design Manual

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14.8.11. LAN Interface

Pin Name
LAN_CLK
LAN_RST#
LAN_RXD[2:0]
LAN_TXD[2:0]
LAN_RSTYSNC
VCCLAN1.5[1:0]
VCCLAN3.3[1:0]
®
Intel 855PM Chipset Platform Design Guide
ICH4-M LAN Interface Recommendations
System
Pull up/Pull down
See Notes
See Notes
See Notes
See Notes
See Notes
See Notes
Platform Design Checklist
Notes
Connect to LAN_CLK on the platform LAN Connect
Device.
See Section 9.9.2 for routing requirements.
If LAN interface is not used, leave the signal
unconnected (NC)
Timing Requirement: Signal should be connected to
power monitoring logic, and should go high no sooner
than 5 ms after both VccLAN3_3 and VccLAN1_5 have
reached their nominal voltages.
NOTE: If ICH4-M LAN controller is NOT used, pull
LAN_RST# down through a 10K resistor.
Connect to LAN_RXD on the platform LAN Connect
Device.
See Section 9.9.2 for routing requirements.
If LAN interface is not used, leave the signal
unconnected (NC)
Connect to LAN_TXD on Platform LAN Connect
Device.
See Section 9.9.2for routing requirements.
If LAN interface is not used, leave the signal
unconnected (NC)
Connect to LAN_RSTSYNC on Platform LAN Connect
Devce.
See Section 9.9.2 for routing requirements.
If LAN interface is not used, leave the signal
unconnected (NC).
If ICH4-M LAN connect interface is used:
Connect VCCLAN1.5[1:0] to the customer designated
1.5VLAN power rail
Connect VCCLAN3.3[1:0] to the customer designated
3.3VLAN power rail
If ICH4-M LAN connect interface is not used:
Connect VCCLAN1.5[1:0] to Vcc1_5
Connect VCCLAN3.3[1:0] to Vcc3_3
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