Figure 70. V Power Planes And Decoupling Example - Intel 855PM Design Manual

Platform Power Requirements
Layer 5 and Layer 6 V
four pairs of V
side (Layer 8). Notice that the vias are placed under the body of the POSCAPs and connect to two small
V and ground floods on the secondary side that connect the vias to the POSCAP pads. This is
CC-MCH
done to minimize the ESL of the POSCAPs in this connection.
In Figure 70 and Figure 71, placement of the POSCAPs on the secondary side is recommended since
Layer 5 and Layer 6 are much closer to the secondary side, thus lower ESL will result from this
connection.
Figure 70. V Power Planes and Decoupling Example
CC-MCH
1.2v
1.5v
1.8v
2.5v
122
floods continue to the VR feed point, they also are via'ed down with the
CC-MCH
and ground vias to connect to the two, 150-µF POSCAPs placed on the secondary
CC-MCH
Primary Side
2x150uF
Secondary
Side
1.2v
VR Feed
1.2v
VR Feed
1.05v
1.2v
AGP
®
Intel 855PM Chipset Platform Design Guide
Layer 5
GND
for PSB
AGP
DDR
HL
Signals
Layer 6
PSB
R