Platform Clock Routing Guidelines; Platform Clock; Ck408 Clock Groups; Platform System Clock Reference - Intel Pentium M Processor Design Manual

Platform Clock Routing Guidelines

4.1

Platform Clock

To minimize jitter, improve routing, and reduce cost, Intel
use a single chip clock solution, the CK408 or CK408B. The difference between the CK408 and
the CK408B is the CK408B provides one additional 100 MHz differential outputs pair. The clock
chip provides three (CK408) or four (CK408B) 100 MHz differential output pairs for the processor
and MCH, including the ITP connector, and six 66 MHz speed clocks that drive all I/O buses.
Figure 7 illustrates the clock architecture.
presents the platform system clock reference. For more information on CK408 or CK408B
compliance, contact your Intel representative.
Table 5.

CK408 Clock Groups

Clock Group Name
Host_CLK
CLK66
CLK33_ICH3-S
CLK14
CLK33
USBCLK
Table 6. Platform System Clock Reference (Sheet 1 of 2)
Clock Group
Host_CLK
CLK66
CLK33_ICH3-S
CLK14
Design Guide
® ®
Intel Pentium M Processor and Intel
Table 5
Frequency (MHz)
100 Processor, Debug Port and MCH
66 MCH, Intel
33 Intel ICH3-S
14.318 Intel ICH3-S and SIO
33 PCI Connector, SIO, BMC, and FWH
48 Intel ICH3-S
CK-408 Pin
CPUCLKT<3>
CPUCLKC<3>
CPUCLKT<0>
CPUCLKC<0>
CPUCLKT<2>
CPUCLKC<2>
66BUF
PCIF
REF0
®
E7501 Chipset Platform
Platform Clock Routing Guidelines
®
E7501 chipset-based systems should
presents the CK408 clock groups.
Receiver
® ®
ICH3-S, and Intel P64H2
Component
Debug Port
Debug Port
Processor
Processor
MCH
MCH
MCH
®
Intel ICH3-S
®
Intel P64H2
Intel ICH3-S
Intel ICH3-S
SIO
PCI Video Down
LPC
4
Table 6
Component Pin Name
CPUCLKT<3>
CPUCLKC<3>
CPUCLKT<0>
CPUCLKC<3>
CPUCLKT<2>
FSB_HCLKINN
66IN
CLK66
CLK66
PCICLK
CLK14
CLOCKl
REFCLK
LPC_CLK
39