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Esd; I/O Apic (I/O Advanced Programmable Interrupt Controller) - Intel 855PM Design Manual

Chipset platform for use with pentium m and celeron m processors
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Finding a common mode choke that meets the designer's needs is a two-step process.
1. A part must be chosen with the impedance value that provides the required noise attenuation. This
is a function of the electrical and mechanical characteristics of the part chosen and the frequency
and strength of the noise present on the USB traces that you are trying to suppress.
2. Once you have a part that gives passing EMI results the second step is to test the effect this part
has on signal quality. Higher impedance common-mode chokes generally have a greater damaging
effect on signal quality, so care must be used when increasing the impedance without doing
thorough testing. Thorough testing means that the signal quality must be checked for low-speed,
full-speed and high-speed USB operation.


Classic USB (1.0/1.1) provided ESD suppression using in line ferrites and capacitors that formed a low
pass filter. This technique doesn't work for USB 2.0 due to the much higher signal rate of high-speed
data. A device that has been tested successfully is based on spark gap technology. Proper placement of
any ESD protection device is on the data lines between the common-mode choke and the USB
connector data pins as shown in Figure 108. Other types of low-capacitance ESD protection devices
may work as well but were not investigated. As with the common mode choke solution, Intel
recommends including footprints for some type of ESD protection device as a stuffing option in case it
is needed to pass ESD testing.
I/O APIC (I/O Advanced Programmable Interrupt
The Intel 82801DBM ICH4-M is designed to be backwards compatible with a number of the legacy
interrupt handling mechanisms as well as to be compliant with the latest I/O (x) APIC architecture. In
addition to implementing two 8259 interrupt controllers (PIC), the ICH4-M also incorporates an
Advanced Programmable Interrupt Controller (APIC) that is implemented via the 3-wire serial APIC
bus that connects all I/O and local APICs. An advancement in the interrupt delivery and control
architecture of the ICH4-M is represented by support for the I/O (x) APIC specification where PCI
devices deliver interrupts as write cycles that are written directly to a register that represents the desired
interrupt. These are ultimately delivered via the serial APIC bus or FSB. Furthermore, on Intel Pentium
M/Intel Celeron M processor-based systems, the ICH4-M has the option to let the integrated I/O APIC
behave as an I/O (x) APIC. This allows the ICH4-M to deliver interrupts in a parallel manner rather than
just a serial one. This is accomplished by I/O APIC writes to a region of memory that is snooped by the
processor and thereby knows what interrupt goes active.
On Intel Pentium M/Intel Celeron M processor-based platforms, the serial I/O APIC bus interface of the
ICH4-M should be disabled. I/O (x) APIC is supported on the platform and the servicing of interrupts is
accomplished via a FSB interrupt delivery mechanism.
The serial I/O APIC bus interface of the ICH4-M should be disabled as follows.
Tie APICCLK directly to ground.
Tie APICD0, APICD1 to ground through a 10-k resistor. (Separate pull-downs are required if
using XOR chain testing)
855PM Chipset Platform Design Guide
I/O Subsystem



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