Agpclk Clock Group; Figure 132. Agpclk To Agp Connector Topology; Figure 133. Agpclk To Agp Device Down Topology - Intel 855PM Design Manual

R
10.2.3.

AGPCLK Clock Group

The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66-MHz clock
input buffer at the AGP device. Note that the goal is to have minimal (~ 0) skew between this clock and
the clocks in the clock group CLK66.

Figure 132. AGPCLK to AGP Connector Topology

Clock
Driver

Figure 133. AGPCLK to AGP Device Down Topology

Clock
Driver
®
Intel 855PM Chipset Platform Design Guide
R1
A
R1
A
Platform Clock Routing Guidelines
B C
Trace on AGP
Card
AGP
Connector
B
AGP
Device
AGP
Device
237