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11.5.1.
DDR Interface Decoupling Guidelines
The following is the recommended decoupling guidelines for the DDR system memory interface.
11.5.1.1.
Intel 855PM MCH VCCSM Decoupling Guidelines
Every Intel 855PM MCH ground and VCCSM power ball in the system memory interface should have
its own via. For the VCCSM pins of the MCH, a minimum of fifteen 0603 form factor 0.1- F high
frequency capacitors is required and must be placed within 150 mils of the MCH package. The fifteen
capacitors should be evenly distributed along the MCH DDR system memory interface and must be
placed perpendicular to the MCH with the power (2.5 V) side of the capacitors facing the MCH. The
trace from the power end of the capacitor should be as wide as possible and it must connect to a 2.5-V
power ball on the outer row of balls on the MCH. Each capacitor should have their 2.5-V via placed
directly over and connected to a separate 2.5-V copper finger, and they should be as close to the
capacitor pad as possible, within 25 mils. The ground end of the capacitors must connect to the ground
flood and to the ground plane through a via. This via should be as close to the capacitor pad as possible,
within 25 mils with as thick a trace as possible.
11.5.1.2.
DDR SO-DIMM System Memory Decoupling Guidelines
Discontinuities in the DDR signal return paths will occur when the signals transition between the
motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity, a minimum of nine
0603 form factor 0.1-µF high frequency bypass capacitors is required between the SO-DIMMs to help
minimize any anticipated return path discontinuities that will be created. The bypass capacitors should
be connected to 2.5 V and ground. The ground trace should connect to a via that transitions to the
ground plane. The ground via should be placed as close to the ground pad as possible. The 2.5-V trace
should connect to a via that transitions to the 2.5-V copper flood and it should connect to the closet 2.5-
V SO-DIMM pin on either the first or second SO-DIMM connector, with a wide trace. The capacitors'
2.5-V traces should be distributed as evenly as possible amongst the two SO-DIMMs. Finally, the 2.5-V
via should be placed as close to the 2.5-V pad as possible.
11.5.2.
2.5-V Power Delivery Guidelines
The 2.5-V power for the Intel 855PM MCH system memory interface and the DDR SO-DIMMs is
delivered around the DDR command, control, and clock signals. Special attention must be paid to the
2.5-V copper flooding to ensure proper MCH and SO-DIMM power delivery. This 2.5-V flood must
extend from the MCH 2.5-V power vias all the way to the 2.5-V DDR voltage regulator and its bulk
capacitors, located at the end of the DDR channel beyond the second SO-DIMM connector. The 2.5-V
DDR voltage regulator must connect to the 2.5-V flood with a minimum of six vias, and the SO-DIMM
connector 2.5-V pins as well as the MCH 2.5-V power vias must connect to the 2.5-V copper flood. The
copper flooding to the MCH should include at least seven fingers to allow for the routing of the DDR
signals and for optimal MCH power delivery. The copper fingers must be kept as wide as possible in
order to keep the loop inductance path from the 2.5-V voltage regulator to the MCH at a minimum. In
the areas where the copper flooding necks down around the MCH make sure to keep these neck down
lengths as short as possible. The 2.5-V copper flooding under the SO-DIMM connectors must
encompass all the SO-DIMM 2.5-V pins and must be solid except for the small areas where the clocks
are routed within the SO-DIMM pin field where they connect to their specified SO-DIMM pins.
®
Intel
855PM Chipset Platform Design Guide
Platform Power Delivery Guidelines
255
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