Topology 2A: Open Drain (Od) Signal Driven By Intel 82801Dbm Ich4-M - Pwrgood; Figure 19. Routing Illustration For Topology 2A; Table 11. Layout Recommendations For Topology 2A - Intel 855PM Design Manual

R
4.1.4.1.4. Topology 2A: Open Drain (OD) Signal Driven by Intel 82801DBM ICH4-M –
PWRGOOD
The Topology 2A OD signal PWRGOOD driven by the Intel 82801DBM ICH4-M (processor CMOS
signal input) should adhere to the following routing and layout recommendations. Table 11 lists the
recommended routing requirements for the PWRGOOD signal of the processor. The routing guidelines
allows the signal to be routed as either micro-strip or strip-lines using 55
impedance. The pull-up voltage for termination resistor Rtt is V
M's CPUPWRGD signal should be routed point-to-point to the processor's PWRGOOD signal. The
routing from the processor's PWRGOOD pin should fork out to both to the termination resistor, Rtt, and
the ICH4-M. Segments L1 and L2 from Figure 19 should not T-split from a trace from the processor
pin.

Figure 19. Routing Illustration for Topology 2A

Rtt

Table 11. Layout Recommendations for Topology 2A

L1
0.5" – 12.0"
0.5" – 12.0"
®
Intel 855PM Chipset Platform Design Guide
VCCP
Pentium M
processor
L2
L2
0" – 3.0"
0" – 3.0"
CCP
Intel
L1
Rtt
330 ± 5%
330 ±5%
FSB Design Guidelines
± 15% characteristic trace
(1.05 V). Note that the Intel ICH4-
Intel
ICH4-M
Transmission Line Type
Micro-strip
Strip-line
55