Page 1 ® Intel 855GM/855GME Chipset Platform Design Guide May 2004 Document Number: 252616-004...
Page 2 The Intel® Pentium® M Processor and Intel® 855GM Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Page 3: Table Of Contents
3.2. Alternate Stack Ups .......................34 Intel Pentium M/Celeron M Front Side Bus Design Guidelines..........37 4.1. Intel Pentium M Processor / Intel Celeron M FSB Design Recommendations .....37 4.1.1. Recommended Stack-up Routing and Spacing Assumptions .......37 4.1.1.1. Trace Space to Trace – Reference Plane Separation Ratio ..37 4.1.1.2.
Page 4 Processor GTLREF Layout and Routing Recommendations......58 4.1.8. AGTL+ I/O Buffer Compensation ..............60 4.1.8.1. Processor AGTL+ I/O Buffer Compensation ........60 4.1.9. Intel Pentium M / Intel Celeron M Front Side Bus Strapping and Debug Port..................... 63 4.1.10. Processor V Design Recommendations......64 CCSENSE SSSENSE 4.2.
Page 5 Data to Strobe Length Matching Requirements......134 7.3.4.4. SDQ to SDQS Mapping ..............135 7.3.4.5. SDQ/SDQS Signal Package Lengths ...........137 7.3.5. Control Signals – SCKE[3:0], SCS#[3:0] .............138 7.3.5.1. Control Signal Topology..............140 7.3.5.2. Control Signal Routing Guidelines ..........142 Intel® 855GM/855GME Chipset Platform Design Guide...
Page 6 Trace Length Requirements for AGP 2X/4X ........ 180 9.2.2.2. Trace Spacing Requirements............180 9.2.2.3. Trace Length Mismatch Requirements ........181 9.2.3. AGP Clock Skew ..................182 9.2.4. AGP Signal Noise Decoupling Guidelines........... 182 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 7 VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......209 11.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....209 11.4.3. USB Power Line Layout Topology ...............209 11.4.4. EMI Considerations..................210 11.4.4.1. Common Mode Chokes ..............210 11.4.5. ESD ......................211 Intel® 855GM/855GME Chipset Platform Design Guide...
Page 8 Termination Plane Capacitance ......... 230 11.9.4. Intel 82562ET/EM Disable Guidelines............231 11.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ....232 11.9.6. General Intel 82562ET / 82562EM / 82551QM / 82540EP Differential Pair Trace Routing Considerations ..............232 11.9.6.1.1.
Page 9 DOTCLK Clock Group..................250 12.2.7. SSCCLK Clock Group..................251 12.2.8. USBCLK Clock Group..................252 12.3. CK-408 Clock Updates for Intel Pentium M Processor and Intel Celeron M Processor Platforms................253 12.4. CK-408 PWRDWN# Signal Connections ..............253 Intel 855GM/GME Chipset Based System Power Delivery Guidelines........255 13.1.
Page 10 USB Selective Suspend ....................277 Reserved, NC, and Test Signals....................279 15.1. Intel Pentium M Processor and Intel Celeron M Processor RSVD Signals ....279 15.2. Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache Processor RSVD Signals .................... 279 15.3.
Page 11 USB Power Checklist....................311 16.8.1. Downstream Power Connection ..............311 16.9. FWH Checklist ......................312 16.9.1. Resistor Recommendations.................312 16.10. LAN / HomePNA Checklist ..................313 16.10.1. Resistor Recommendations (for 82562ET / 82562EM) .......313 16.10.2. Decoupling Recommendations ..............314 Schematics ..........................315 Intel® 855GM/855GME Chipset Platform Design Guide...
Page 12 Figure 1. Intel Pentium M Processor and Intel 855GM Chipset Block Diagram...... 26 Figure 2. Intel Pentium M, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache, Intel Celeron M Processor and 855GME Chipset System Block Diagram ....30 Figure 3.
Page 13 Figure 93. Connection Requirements for Secondary IDE Connector ........197 Figure 94. PCI Bus Layout Example ..................200 Figure 95. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......... 201 Figure 96. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ......... 202 Figure 97.
Page 14 Figure 115. Intel 82562ET / Intel 82562EM Termination ............228 Figure 116. Critical Dimensions for Component Placement..........229 Figure 117. Termination Plane....................231 Figure 118. Intel 82562ET/EM Disable and Power Down Circuitry ........231 Figure 119. Trace Routing ..................... 233 Figure 120. Ground Plane Separation ................... 235 Figure 121.
Page 15 Figure 156. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local Voltage Divider Circuit for VSWING/VREF............307 Figure 157. External Circuitry for the RTC ................308 Figure 158. Good Downstream Power Connection............... 312 Figure 159. LAN_RST# Design Recommendation ............... 313 Intel® 855GM/855GME Chipset Platform Design Guide...
Page 16 Mapping ........................45 Table 7. Processor PSB Source Synchronous Address Signal Routing Guidelines....46 Table 8. Intel Pentium M / Intel Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths................... 47 Table 9. Asynchronous AGTL+ Nets ..................49 Table 10.
Page 17 Table 92. Bus Capacitance/Pull-Up Resistor Relationship ........... 215 Table 93. RTC Routing Summary ..................219 Table 94. LAN Component Connections/Features ............... 224 Table 95. LAN Design Guide Section Reference..............225 Table 96. LAN LOM Routing Summary................. 226 Intel® 855GM/855GME Chipset Platform Design Guide...
Page 18 Table 114. Analog Supply Filter Requirements ..............272 Table 115. ICH4-M Decoupling Requirements ..............273 Table 116. Processor RSVD and TEST Signal Pin-Map Locations ........279 Table 117. Intel 855GM/GME Chipset GMCH RSVD and NC Signal Pin-Map Locations ..280 ® Intel...
Page 19 Updates Include: September 2003 • Added 855GME design guidelines Updates Include: January 2004 • Added Intel Celeron M processor support Updates include: May 2004 • Added section 7 Memory Down/Micro-DIMM design guidelines • Added section 9 AGP Port Design guidelines ®...
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Page 21: Introduction
Any plane-split, void or cutout in a VCC or GND plane is referred to as an anti-etch Alert Standards Format Bit Error Rate Intel Pentium M/ Pentium M on 90 nm Process with 2 MB L2 Cache/Celeron M Front Side Bus –Processor to GMCH interface. Common Mode Choke...
Page 22 Introduction Convention/Terminology Definition components can communicate Serial Presence Detect Suspend-To-Disk Suspend-To-Ram Total Cost of Ownership Time Division Multiplexed UBGA Micro Ball Grid Array Universal Serial Bus Voltage Regulator Module ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 23: Referenced Documents
Contact your Intel Field Representative JEDEC Standard, JESD79, Double Data Rate (DDR) Contact your Intel Field Representative SDRAM Specification ® Intel DDR 200/266/333 JEDEC Spec Addendum http://developer.intel.com PC2100 DDR SDRAM Unbuffered SO-DIMM Reference http://developer.intel.com Design Specification ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 24 Introduction This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 25: System Overview
The integrated Wi-Fi Certified Intel PRO/Wireless 2100 Network Connection has been designed and validated to work with all of the Intel Centrino™ mobile technology components and is able to connect to 802.11b Wi-Fi certified access points. It also supports advanced wireless LAN security including Cisco* LEAP, 802.1X, and WEP in addition to providing software-upgradeable support for future...
Page 26: Intel 855Gm Platform Component Features
M Processor and Intel Celeron M Processor • On-die primary 32-kbyte, instruction cache and 32-kbyte, write-back data cache • On-die 1-MB second level cache; On-die 512-kB second level cache (Intel Celeron M Processor) • Supports Streaming SIMD Extensions 2 (SSE2) •...
Page 27: Intel ® 855Gm Chipset Graphics Memory Controller Hub (Gmch)
System Overview  Intel Celeron M processor: 1.356 V (Standard Voltage core version), 1.004 V (Ultra-  Low Voltage core version)  VCCA (1.8 V):  VCCP (1.05 V) ® 2.2.2. Intel 855GM Chipset Graphics Memory Controller Hub (GMCH) 2.2.2.1.
Page 28: Package/Power
• AC’97 2.2 / 2.3 Interface • Alert-On-LAN* • IRQ Controller • Package/Power  421-pin, BGA package (31 mm x 31 mm)  VCC1_5 (1.5 V main logic voltage), VCC3_3 (3.3 V main I/O voltage) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 29: Intel ® Pro/Wireless Network Connection
LAN connections • Intel PROSet software supports Cisco, Check Point*, Microsoft* and Intel VPN connections† • Intel PROSet software with ad hoc connection wizard support provides a simple interface for setting up ad hoc networks • Intel Wireless Coexistence System support enables reduced interference between Intel PRO/Wireless and certain Bluetooth* devices •...
Page 30: Intel 855Gme Platform Component Features
All features in Intel 855GM chipset based system are supported in the Intel 855GME chipset based system as well. Figure 2. Intel Pentium M, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache, Intel Celeron M Processor and 855GME Chipset System Block Diagram Intel®...
Page 31: Intel 855Gme Chipset Graphics Memory Controller Hub (Gmch)
2.3.2. Intel 855GME Chipset Graphics Memory Controller Hub (GMCH) All chipset and graphics features of Intel 855GM chipset GMCH is supported in Intel 855GME chipset GMCH. This section lists the additional enhancements. • Integrated System Memory DRAM controller  Supports up to two double-sided SO-DIMMs (four rows populated) with unbuffered PC1600/PC2100/PC2700 DDR-SDRAM (ECC is not supported) ...
Page 32 System Overview This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 33: General Design Considerations
Nominal Board Stack-Up The Intel 855GM/GME chipset based platforms require a board stack-up yielding a target impedance of 55 Ω ± 15%. An example of an 8-layer board stack-up is shown in Figure 3. The left side of the figure illustrates the starting dimensions of the metal and dielectric material thickness as well as drawn trace width dimensions prior to lamination, conductor plating, and etching.
Page 34: Alternate Stack Ups
To guarantee this, both planes surrounding strip-lines should be GND. 4. Intel recommends that high-speed signal routing be done on internal, strip-line layers. 5. For high-speed signals transitioning between layers next to the component, the signal pins should be accounted for by the GND stitching vias that would stitch all the GND plane layers in that area ®...
Page 35 7. If Intel’s recommended stackup guidelines are not used, then the OEM is liable for all aspects of their board design (i.e. understanding impacts of SI and power distribution).
Page 36 General Design Considerations This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 37: Intel Pentium M/Celeron M Front Side Bus Design Guidelines
Intel Pentium M Processor / Intel Celeron M FSB Design Recommendations For proper operation of the Intel Pentium M / Intel Celeron M processor and the GMCH PSB interface, it is necessary that the system designer meet the timing and voltage specification of each component.
Page 38: Trace Space To Trace Width Ratio
For details on minimum motherboard trace length requirements, please refer to Section 4.1.2.1 and Table 2 for more details. Intel recommends routing these signals on the same internal layer for the entire length of the bus. If routing constraints require routing of these signals with a transition to a different layer, a minimum of one ground stitching via for every two signals should be placed within 100 mils of the signal transition vias.
Page 39: Processor Common Clock Signal Package Length Compensation39
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Table 2 summarizes the list of common clock and key routing. RESET# (CPURST# of GMCH) is also a common clock signal but requires a special treatment for the case where an ITP700FLEX debug port is used.
Page 40: Source Synchronous Signals General Routing Guidelines
Intel Pentium M/Celeron M Front Side Bus Design Guidelines BR0# = X mils board trace + 336 CPU PKG + 465 GMCH PKG = 2212 pad-to-pad length Therefore: X = BR0# board trace = 2212 - 336 - 465 = 1411 pin to pin length.
Page 41 Intel Pentium M/Celeron M Front Side Bus Design Guidelines requires careful attention to their routing considerations. The following guidelines should be strictly adhered to, to guarantee robust high frequency operation of these signals. Source synchronous data and address signals and their associated strobes are partitioned into groups of signals.
Page 42: Figure 7. Layer 6 Psb Source Synchronous Signals Gnd Referencing To Layer 5
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 7. Layer 6 PSB Source Synchronous Signals GND Referencing to Layer 5 In a similar way, Figure 8 illustrates a recommended layout and stack-up example of how another group of PSB source synchronous DATA and ADDRESS signals can reference ground planes on both Layer 2 and Layer 4.
Page 43: Source Synchronous Signal Length Matching Constraints
4.1.3.2. Package Length Compensation The Intel Pentium M / Intel Celeron M processor package length does not need to be accounted for in the motherboard routing since the processor has the source synchronous signals and the strobes length matched within the group inside the package routing. However trace length matching of the GMCH...
Page 44: Source Synchronous - Data Group
±100 mils of the associated strobes. Only the Intel Pentium M / Intel Celeron M processor has the package trace equalization for signals within each data and address group. The GMCH does not have the package trace equalization for signals within each data and address group.
Page 45: Source Synchronous - Address Group
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Table 5. Processor System Bus Source Synchronous Data Signal Routing Guidelines Signal Names Total Trace Length Nominal Spacing Transmission Impedance & Width Line Type ( Ω ) Data Data Data Data...
Page 46: Intel Pentium M / Intel Celeron M Processor And Intel 855Gm/Gme Chipset Gmch Psb Signal Package Lengths
Intel Pentium M / Intel Celeron M Processor and Intel 855GM/GME Chipset GMCH PSB Signal Package Lengths Table 8 lists the preliminary package trace lengths of the Intel Pentium M / Intel Celeron M processor and the Intel 855GM/GME chipset GMCH for the source synchronous data and address signals. The processor PSB package signals within the same group are routed to the same package trace length, but the GMCH package signals within the same group are not routed to the same package trace length.
Page 47: Table 8. Intel Pentium M / Intel Celeron M Processor And Gmch Source Synchronous Fsb Signal Package Lengths
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Table 8. Intel Pentium M / Intel Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths GMCH GMCH Signal Package GMCH Package Signal Package GMCH Package Signal Signal Group...
Page 48 Intel Pentium M/Celeron M Front Side Bus Design Guidelines GMCH GMCH Signal Package GMCH Package Signal Package GMCH Package Signal Signal Group Length Signal Name Length Group Length Signal Name Length Name Name (mils) (mils) (mils) (mils) DSTBP[2]# HDSTBP[2]# DSTBP[3]#...
Page 49: Asynchronous Signals
VCCP, the reliability and power consumption of the processor may be affected. Therefore, it is very important to follow the recommended pull-up voltage for these signals. All signals must meet the AC and DC specifications as documented in the Mobile Intel® Pentium® M Processor Datasheet. Table 9. Asynchronous AGTL+ Nets...
Page 50: Topology 1A: Open Drain (Od) Signals Driven By The Processor - Ierr
Rtt is VCCP (1.05 V). Intel recommends that the FERR# signal of the processor be routed to the FERR# signal of the ICH4-M. THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the ICH4-M or any optional system receiver.
Page 51: Topology 1C: Open Drain (Od) Signals Driven By The Processor - Prochot
Intel Pentium M/Celeron M Front Side Bus Design Guidelines dampening resistor R1 in Topology 1B. Thus, it is important to note that R1 will no longer be required in such a topology. Figure 10. Routing Illustration for Topology 1B VCCP ICH4-M (or sys.
Page 52: Topology 2A: Open Drain (Od) Signals Driven By Ich4-M - Pwrgood
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 11. Routing Illustration for Topology 1C (System receiver) V_IO_RCVR VCCP 3904 3904 Table 12. Layout Recommendations for Topology 1C Transmission 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 k Ω ± 5% 330 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5”...
Page 53: Topology 2B: Cmos Signals Driven By Ich4-M - Dpslp
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Table 13. Layout Recommendations for Topology 2A Transmission Line Type 330 Ω ± 5% 0.5” – 12.0” 0” – 3.0” Micro-strip 330 Ω ±5% 0.5” – 12.0” 0” – 3.0” Strip-line 4.1.4.5.
Page 54: Topology 3: Cmos Signals Driven By Ich4-M To Cpu And Fwh - Init
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 14. Routing Illustration for Topology 2C ICH4-M Table 15. Layout Recommendations for Topology 2C Transmission Line Type 0.5” – 12.0” Micro-strip 0.5” – 12.0” Strip-line 4.1.4.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT# The signal INIT# should adhere to the following routing and layout recommendations.
Page 55: Voltage Translation Logic
16 should be used without exception. With the low 1.05-V signaling level of the Intel Pentium M / Intel Celeron M Front Side Bus, the voltage translation circuit provides ample isolation of any transients or signal reflections at the input of transistor Q1 from reaching the output of transistor Q2.
Page 56: Figure 17. Processor Reset# Signal Routing Topology With No Itp700Flex Connector
Intel Pentium M/Celeron M Front Side Bus Design Guidelines termination of the AGTL+ buffers on both the processor and the GMCH provide proper signal quality for this connection. This is the same case as for the other common clock signals listed Section 4.1.2.
Page 57: Processor Reset# Routing Example
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector L2 + L3 Rs = 22.6 Ω ± 1% Rtt = 220 Ω ± 5% 1.0” – 6.0” 6.0” max 0.5” max 4.1.5.1.
Page 58: Processor Gtlref Layout And Routing Recommendations
4.1.7. Processor GTLREF Layout and Routing Recommendations There is one AGTL+ reference voltage pin on the Intel Pentium M / Intel Celeron M processor, GTLREF, which is used to set the reference voltage level for the AGTL+ signals (GTLREF). The reference voltage must be supplied to the GTLREF pin.
Page 59: Figure 21. Processor Gtlref Voltage Divider Network
GTLREF routing to create splits or discontinuities in the reference planes of the Processor System Bus signals). RSVD signal pins E26, G1, and AC1 are to be left unconnected on Intel® Pentium® M and Intel Celeron M processor-based systems.
Page 60: Agtl+ I/O Buffer Compensation
4.1.8. AGTL+ I/O Buffer Compensation The Intel Pentium M / Intel Celeron M processor has 4 pins, COMP[3:0], and the GMCH has 2 pins, HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the GMCH requires two special reference voltage generation circuits to pins HSWNG[1:0] for the same purpose described above.
Page 61: Figure 23. Processor Comp[2] & Comp[0] Resistive Compensation
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 23. Processor COMP[2] & COMP[0] Resistive Compensation COMP[2] COMP[0] 27.4 Ω +/- 1% 27.4 Ω +/- 1% Figure 24. Processor COMP[3] & COMP[1] Resistive Compensation COMP[3] COMP[1] 54.9 Ω +/- 1% 54.9 Ω...
Page 62: Figure 25. Processor Comp[3:0] Resistor Layout
Intel Pentium M/Celeron M Front Side Bus Design Guidelines compensation resistors on the secondary side. The use of 18-mil wide dog bones and traces is used to achieve the Zo = 27.4-Ω target to ensure proper operation of the PSB. See Figure 27 for more details.
Page 63: Intel Pentium M / Intel Celeron M Front Side Bus Strapping And Debug Port
Intel Pentium M / Intel Celeron M Front Side Bus Strapping and Debug Port The Intel Pentium M / Intel Celeron M processor and GMCH both have pins that require termination for proper component operation. 1. For the processor, a stuffing option should be provided for the TEST[3:1] pin to allow a 1 kΩ ±...
Page 64: Intel System Validation Debug Support
CCSENSE SSSENSE The VCCSENSE and VSSSENSE signals of the Intel Pentium M processor and Intel Celeron M provide isolated, low impedance connections to the processor’s core power (VCC) and ground (VSS). These pins can be used to sense or measure power (VCC) or ground (VSS) near the silicon with little noise.
Page 65: Itp Support
4.2.2.1. Background/Justification The Intel Pentium M / Intel Celeron M FSB Logic Analyzer probe (LAI) is the second key tool. It is widely used by various validation, test, and debug groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers) and is needed to debug BIOS, logic, signal integrity, general software, and general hardware issues involving CPUs, chipsets, SIOs, PCI devices, and other hardware.
Page 66: Implementation
Details from Agilent Corporation on the FSB LAI mechanicals (i.e. design guide with keepout volume info) are available for ordering. Please contact your local Intel field representative on how to obtain the latest design info. See Section 4.3.3 for more details.
Page 67: Figure 29. Itp700Flex Debug Port Signals
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 29. ITP700FLEX Debug Port Signals BCLKp BCLKn 1.05v 1.05v CK408 Processor 150 Ω 39.2 Ω ITPCLK[1:0] BaniasCLK[1:0] BCLK[1:0] TRST# TRST# TRST# TRST# 1.05v GMCHCLK[1:0] 680 Ω 0.1uF VTAP 27.4 Ω...
Page 68 Intel Pentium M/Celeron M Front Side Bus Design Guidelines termination guarantee proper signal quality for the BPM[4:0]# signals. Due to the length of the ITP700FLEX cable, the length L2 of the BPM[4:0]# signals on the motherboard should be limited to be shorter than 6.0 inches.
Page 69: Itp Signal Routing Example
Intel Pentium M/Celeron M Front Side Bus Design Guidelines DBA# is an optional system signal that can be used to indicate to the system that the ITP/TAP port is being used. If not implemented, this signal can be left as no connect. If implemented, it should be routed with a 150 Ω...
Page 70: Itp_Clk Routing To Itp700Flex Connector
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Note that the V (1.05 V) power delivery continues from the processor socket cavity on the secondary side of the motherboard through the pin field as shown on the right side of Figure 30. Three V...
Page 71: Figure 30. Itp700Flex Signals Layout Example
Intel Pentium M/Celeron M Front Side Bus Design Guidelines Figure 30. ITP700FLEX Signals Layout Example Primary Side Secondary Side 1.05v 150 Ω VCCA=1.8v TRST# 1.05v 27.4 Ω 1.05v BPM[5:0]# 680 Ω VTT, VTAP 39.2 Ω DBR# 0.1uF 22.6 Ω 220 Ω...
Page 72: Itp700Flex Design Guidelines For Production Systems
The ITP interposer card is an additional component that integrates the processor socket along with ITP700 connector on a single interposer card that is compatible with the 478-pin Intel Pentium M / Intel Celeron M processor socket.
Page 73: Itp Interposer Design Guidelines For Production Systems
Intel Pentium M/Celeron M Front Side Bus Design Guidelines also requires the use of a pair of 33-Ω ± 5% series resistors placed within 0.5 inches of the clock chip output pins and followed by a pair of 49.9-Ω ± 1% termination resistors to ground. The majority of the ITP_CLK differential serpentine routing takes place on internal Layer 6 below the PSB address signal routing.
Page 74: Logic Analyzer Interface (Lai)
The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the Intel Pentium M processor / Intel Celeron M processor in the 478-pin package plugs into a socket on the LAI. Cabling this part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer.
Page 75: Intel® Mobile Voltage Positioning Iv General Description
Mobile Voltage Positioning IV General Description Please contact your Intel Field Representative for more information on the electrical requirements for the DC-to-DC Voltage Regulator for the Intel Pentium M processor / Intel Celeron M processor. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 76: System Memory Design Guidelines (Ddr-Sdram) For So-Dimm Configuration
(DDR-SDRAM) for SO-DIMM configuration The Intel 855GM/GME chipset GMCH Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 20 summarizes the ®...
Page 77: Length Matching And Length Formulas
A simple summary of the length matching formulas for each signal group is provided in the tables below. Table 21. Intel 855GM Chipset GMCH DDR 200/266 Length Matching Formulas Signal Group Minimum Length...
Page 78: Package Length Compensation
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 79: Memory Clock Routing Guidelines
Match total length to +/- 10 mils (see Section 6.3.3.1) Match all SO-DIMM0 clocks to X0 +/- 25 mils (see Figure 34) Clock to Clock Length Matching (Total Length) Match all SO-DIMM1 clocks to X1 +/- 25 mils (see Figure 34) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 80: Clock Length Matching Requirements
The first step in determining the routing lengths for clocks and all other clock relative signal groups is to establish the target length for each SO-DIMM clock group. These target lengths are shown as X0 and ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 81: Clock Reference Lengths
SCK4 Length = X1 GMCH SCK4# SCK#4 Length = X1 SCK5 SCK5 Length = X1 SCK#5 Length = X1 SCK#5 Length = X1 +/-25mils Note: All lengths are measured from GMCH die-pad to SO-DIMM1 connector pads. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 82: Clock Package Length Table
SCK/SCK# exactly, or alternatively the average package length can be used for both outputs of a pair and length tuning done with respect to the motherboard portion only. 6.3.3.4. Clock Routing Example Figure 35 is an example of a board routing for the clock signal group. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 83: Data Signals - Sdq[71:0], Sdm[8:0], Sdqs[8:0]
SO-DIMM1, then transition the signal back out to an external layer and connect to the appropriate pad of SO-DIMM1. Connection to the termination resistor should be via the same internal layer with a transition back to the external layer near the resistor. External trace lengths should be minimized. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 84: Data Bus Topology
The table and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals. Intel recommends that the full data bus SDQ[71:0], mask bus SDM[8:0], and strobe signals SDQS[8:0] be routed on the same internal signal layer. It is required that the SDQ byte group and the associated SDM and SDQS signals within a byte lane be routed on the same internal layer.
Page 85: Sdqs To Clock Length Matching Requirements
GMCH die-pad and the SO-DIMMs must fall within the range defined in the formulas below. See the clock Section for the definition of the clock reference length. Refer to Figure ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 86 Length matching is only performed from the GMCH to the SO-DIMMs, and does not involve the length of L4, which can vary over its entire range. Intel recommends that routing segment length L3 between SO-DIMM0 to SO-DIMM1 be held fairly constant and equal to the offset between clock reference lengths X0 and X1.
Page 87: Data To Strobe Length Matching Requirements
Y = SDQ, SDM total length, including package length, within same byte lane as show in Figure 38, where: ( X – 25 mils ) ≤ Y ≤ ( X + 25 mils ) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 88: Sdq To Sdqs Mapping
Table 27. SDQ/SDM to SDQS Mapping Signal Mask Relative To SDQ[7:0] SDM[0] SDQS[0] SDQ[15:8] SDM[1] SDQS[1] SDQ[23:16] SDM[2] SDQS[2] SDQ[31:24] SDM[3] SDQS[3] SDQ[39:32] SDM[4] SDQS[4] SDQ[56:40] SDM[5] SDQS[5] SDQ[55:48] SDM[6] SDQS[6] SDQ[63:56] SDM[7] SDQS[7] SDQ[71:64] SDM[8] SDQS[8] ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 89: Sdq/Sdqs Signal Package Lengths
SDQS motherboard trace as required to achieve the overall length matching requirements defined in the prior Sections. Table 28. Memory SDQ/SDM/SDQS Package Lengths Signal Length Signal Length Signal Length Number Number Number (mils) (mils) (mils) SDQ_00 SDQ_24 AH10 SDQ_48 AE23 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 90 AG22 SDQ_71 AF17 SDM_0 SDQS_0 SDM_1 SDQS_1 SDM_2 SDQS_2 SDM_3 AH12 SDQS_3 AE12 SDM_4 AD19 SDQS_4 AH17 SDM_5 AD21 SDQS_5 AE21 SDM_6 AD24 SDQS_6 AH24 SDM_7 AH28 SDQS_7 AH27 SDM_8 AH15 SDQS_8 AD15 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 91: Memory Data Routing Example
(CKE) signal per SO-DIMM physical device row. Two chip select and two clock enable signals will be routed to each SO-DIMM. Refer to Table 29 for the CKE and CS# signal to SO-DIMM mapping. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 92: Control Signal Topology
All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 93: Control Signal Routing Guidelines
3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel termination resistor. 4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 94: Control To Clock Length Matching Requirements
A nominal CS/CKE package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 95: Figure 41. Control Signal To Clock Trace Length Matching Diagram
SO-DIMM connector pads. SO-DIMM0 SO-DIMM1 GMCH Package SCS#[3:2] SCKE[3:2] CNTRL Length = Y1 GMCH SCK[5:3] Clock Ref. Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pads. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 96: Memory Control Routing Example
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration 6.3.5.4. Memory Control Routing Example Figure 42 is an example of a board routing for the Control signal group. Figure 42. Control Signals Group Routing Example From GMCH Control Signals ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 97: Control Group Package Length Table
Rt. Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous.
Page 98: Command Topology 1 Routing Guidelines
SO-DIMM pad spacing Trace Length L4 – Second SO-DIMM Via to Parallel Max = 1.5 inches Resistor Pad 10 Ω ± 5% Series Termination Resistor (Rs) 56 Ω ± 5% Parallel Termination Resistor (Rt) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 99: Command Topology 1 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 100: Figure 44. Topology 1 Command Signal To Clock Trace Length Matching Diagram
SO-DIMM1 SO-DIMM0 SMAA[12:6,3,0] SBA[1:0], GMCH Package RAS#, CAS#, CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 101: Command Topology 2
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non- DDR related signals. Command signals should be routed on inner layers with minimized external trace lengths. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 102: Command Topology 2 Routing Guidelines
4. It is possible to route using 3 vias if one via is shared that connects to the SO-DIMM0 pad and series termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 103: Command Topology 2 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 104: Figure 46. Topology 2 Command Signal To Clock Trace Length Matching Diagram
SO-DIMM0 SMAA[12:6,3,0] SBA[1:0], SRAS#, SCAS#, SWE# GMCH Package CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 105: Command Topology 2 Routing Example
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration 6.3.6.7. Command Topology 2 Routing Example Figure 47 is an example of a board routing for the Command signal group. Figure 47. Example of Command Signal Group From GMCH Command Signals ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 106: Command Topology 3
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non- DDR related signals. Command signals should be routed on inner layers with minimized external trace lengths. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 107: Command Topology 3 Routing Guidelines
4. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 108: Command Topology 3 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 109: Figure 49. Topology 3 Command Signal To Clock Trace Length Matching Diagram
SMAA[12:6,3,0] to termination SBA[1:0], GMCH Package RAS#, CAS#, CMD Length = Y1 GMCH SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 110: Command Group Package Length Table
Table 35. Command Group Package Lengths Pkg Length Signal Pin Number (mils) SMA[0] AC18 SMA[3] AD17 SMA[6] SMA[7] SMA[8] SMA[9] SMA[10] AC19 SMA[11] SMA[12] SBA[0] AD22 SBA[1] AD20 SCAS# AC24 SRAS# AC21 SWE# AD25 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 111: Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]
• External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths.
Page 112: Cpc Signal Topology
Max = 4.5 inches for DDR333 Trace Length L2 – SO-DIMM Via to Parallel Termination Resistor Max = 2.0 inches 56 Ω ± 5% Parallel Termination Resistor (Rt) Maximum Recommended Motherboard Via Count Per Signal ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 113: Cpc To Clock Length Matching Requirements
Figure 51 on the following page depicts the length matching requirements between the CPC signals and clock. A nominal CPC package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 114: Cpc Group Package Length Table
Table 38. CPC Group Package Lengths Pkg Length Pkg Length Signal Signal Number (mils) Number (mils) SMA[1] AD14 SMAB[1] AD16 SMA[2] AD13 SMAB[2] AC12 SMA[4] AD11 SMAB[4] AF11 SMA[5] AC13 SMAB[5] AD10 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 115: Feedback - Rcvenout#, Rcvenin
SDQ[71:64], SDQS8, SDM8 and the two differential clock pairs that are not routed to the SO-DIMMs. The 855GM/GME chipset GMCH provides the capability to enable and disable the CS/CKE control and SCK signals to unpopulated SO-DIMMs to save power. Although DDR SO-DIMM connectors may provide motherboard lands for three clock pairs, non-ECC SO-DIMMs only require two pairs.
Page 116: Ddr Memory Ecc Functionality Disable
SO-DIMMs be disabled when the system is populated with only non-ECC or a combination of ECC and non-ECC memory. Please see the RS – Intel 855GM/GME (Montara-GM/GM+) Chipset GMCH BIOS Specification for information on memory initialization and register programming.
Page 117: Ets# Usage Model
DDR system memory. Intel is currently in the process of enabling this feature on the Intel 855GM/GME chipset GMCH and is actively engaging with thermal sensor vendors to ensure compatibility and suitability of vendors’...
Page 118: Figure 52. Ddr Memory Thermal Sensor Placement
15 mm (0.6 inches) of the outline/SO-DIMM shadow. Again, this assumes negligible effects from airflow. Please refer to the Intel (R) 855GM (Montara-MG) Chipset Mobile Thermal Design Guide for more details.
Page 119 System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 120: System Memory Design Guidelines (Ddr-Sdram) For Memory Down Configuration
DIMM Reference Design Specification and Table 39 shows the supported memory configurations for Memory Down. Table 39. Supported Memory Configurations - Micro-DIMM Device Type Module Bus Device Width #Devices Physical Capacity Width Banks TSOP 32-256 MB 32-512 MB 64 MB – 1 GB ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 121: Table 40. Supported Memory Configurations - Memory Down
For an 8-BGA device configuration, four devices are placed on one side of the motherboard and four on the opposite side. The 855GM/GME chipset Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals.
Page 122: Length Matching And Length Formulas
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the ®...
Page 123: Topologies And Routing Guidelines
7.3.2. Clock Topology Diagram The 855GM/GME GMCH provides 6 differential clock output pairs. The motherboard clock routing topology is shown below for reference. Refer to the routing guidelines in Table 44 on the follow page for detailed length and spacing rules for each segment.
Page 124: Figure 55. Ddr Clock Routing To Memory Down Two Load Bga
The clock signals should be routed as closely coupled differential pairs over the entire length. Spacing to other DDR signals should not be less than 20 mils. Isolation spacing to non-DDR signals should be 25 mils. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 125: Ddr Clock Routing Guidelines
Match total length to +/- 10 mils (see Section 7.3.3.1) Match all Micro-DIMM clocks to X0 +/- 25 mils (see section 7.3.3.2) Clock to Clock Length Matching (Total Length) Match all Memory Down clocks to X1 +/- 25 mils (see section 7.3.3.2) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 126: Clock Length Matching Requirements
The total length including package should be matched to within ± 25 mils of each other, as shown in the Length Range Formula for Micro-DIMM: ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 127: Clock Reference Lengths
X1 = SCK/SCK#[4:3] P1 + L1 + L2 + L3 + L4 (see Figure 55) = SCK/SCK#[4:3] P1 + L1 + L2 + L3 + L4 + L5 (see Figure 56 and Figure 57) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 128: Figure 58. Ddr Clock Trace Length Matching Diagram
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration Figure 58. DDR Clock Trace Length Matching Diagram ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 129: Clock Package Length Table
• At the Micro-DIMM connector, the signal should transition to an external layer and connect to the appropriate pad on the connector. • After the Micro-DIMM transition, continue to route the signal on the same internal layer until transitioning back to an external layer at the series resistor. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 130 The table and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals. Intel recommends that the full data bus SDQ[63:0], mask bus SDM[7:0], and strobe signals SDQS[7:0] be routed on the same internal signal layer. It is required that the SDQ byte group and the associated SDM and SDQS signals within a byte lane be routed on the same internal layer.
Page 131: Data Bus Topology
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR related signals. Data signals should be routed on inner layers with minimized external trace lengths. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 132: Table 46. Data Signal Group Routing Guidelines
1. Power distribution vias from Rt to Vtt are not included in this count. 2. The overall minimum and maximum length to the Micro-DIMM and Memory Down must comply with clock length matching requirements. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 133: Sdqs To Clock Length Matching Requirements
L3, which can vary over its entire range. Note that a nominal SDQS package length of 750 mils can be used to estimate motherboard lengths prior to performing package length compensation. Refer to Section 7.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 134: Data To Strobe Length Matching Requirements
Length range formula for SDQ and SDM, X = SDQS total length, including package length, as defined previously Y = SDQ, SDM total length, including package length, within same byte lane as shown in Figure ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 135: Sdq To Sdqs Mapping
Table 47. SDQ/SDM to SDQS Mapping Signal Mask Relative To SDQ[7:0] SDM[0] SDQS[0] SDQ[15:8] SDM[1] SDQS[1] SDQ[23:16] SDM[2] SDQS[2] SDQ[31:24] SDM[3] SDQS[3] SDQ[39:32] SDM[4] SDQS[4] SDQ[56:40] SDM[5] SDQS[5] SDQ[55:48] SDM[6] SDQS[6] SDQ[63:56] SDM[7] SDQS[7] ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 136: Figure 62. Sdq/Sdm To Sdqs Trace Length Matching Diagram
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration Figure 62. SDQ/SDM to SDQS Trace Length Matching Diagram ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 137: Sdq/Sdqs Signal Package Lengths
SDQ_18 SDQ_50 AE24 SDQ_19 AG10 SDQ_51 AH25 SDQ_20 SDQ_52 AG23 SDQ_21 SDQ_53 AF23 SDQ_22 AF10 SDQ_54 AF25 SDQ_23 AE11 SDQ_55 AG25 SDQ_24 AH10 SDQ_56 AH26 SDQ_25 AH11 SDQ_57 AE26 SDQ_26 AG13 SDQ_58 AG28 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 138: Control Signals - Scke[3:0], Scs#[3:0]
SCKE[3] and SCS#[3] should be left as no connects. Refer to Table 49 for the CKE and CS# signal to Micro-DIMM or Memory Down mapping. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 139: Table 49. Control Signal To Micro-Dimm/Memory Down Mapping
SDRAM device (4 TSOP SDRAMs) or two SDRAMs (8 BGAs). External trace lengths should be minimized. All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 140: Control Signal Topology
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration 7.3.5.1. Control Signal Topology Figure 63. Control Signal Routing GMCH to Micro-DIMM Pad Figure 64. Control Signal Routing GMCH to Memory Down 1x16 4 Load TSOP ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 141: Figure 65. Control Signal Routing Gmch To Memory Down 1X16/2X16 4 Load Bga
The control signals should be routed using 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals. Control signals should be routed on inner layers with minimized external trace lengths. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 142: Control Signal Routing Guidelines
Maximum Recommended Motherboard Via Count Per Signal CTRL to SCK/SCK# [4,3,1,0] Length Matching Requirements See length matching Section 7.3.5.3 and Figure 67. NOTE: The overall maximum and minimum length to the Micro-DIMM must comply with clock length matching requirements. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 143: Control To Clock Length Matching Requirements
A nominal CS/CKE package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section Note: for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 144: Control Group Package Length Table
Table 51. Control Group Package Lengths Package Length Signal Pin Number (mils) SCS#[0] AD23 SCS#[1] AD26 SCS#[2] AC22 SCS#[3] AC25 SCKE[0] SCKE[1] SCKE[2] SCKE[3] AC10 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 145: Command Signals - Smaa[12:6,3,0], Sba[1:0], Sras#, Scas#, Swe
Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE# The Intel 855GM GMCH chipset command signals, SMA[12:0], SBA[1:0], SRAS#, SCAS#, and SWE# clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The GMCH drives the command and clock signals together, with the clocks crossing in the valid command window. A series...
Page 146: Figure 68. Cmd Signal Routing Gmch To Micro-Dimm And Mem Down Tsop 4 Load
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration Figure 68. CMD Signal Routing GMCH to Micro-DIMM and Mem Down TSOP 4 Load Figure 69. CMD Signal Routing GMCH to Micro-DIMM and Mem Down BGA 4 Load ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 147: Figure 70. Cmd Signal Routing Gmch To Micro-Dimm And Memory Down Bga 8-Load
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR related signals. Command signals should be routed on inner layers with minimized external traces. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 148: Command Topology Routing Guidelines
2. Power distribution vias from Rt to Vtt are not included in this count. 3. The overall maximum and minimum length to the Micro-DIMM and Memory Down must comply with clock length matching requirements. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 149: Command Topology Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Note: for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 150: Figure 71. Topology 1 Command Signal To Clock Trace Length Matching Diagram
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration Figure 71. Topology 1 Command Signal to Clock Trace Length Matching Diagram ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 151: Command Group Package Length Table
Table 53. Command Group Package Lengths Pkg Length Signal Pin Number (mils) SMAA_00 AC18 SMAA_03 AD17 SMAA_06 SMAA_07 SMAA_08 SMAA_09 SMAA_10 AC19 SMAA_11 SMAA_12 SBA[0] AD22 SBA[1] AD20 SCAS# AC24 SRAS# AC21 SWE# AD25 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 152: Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]
SDRAM device (4 TSOP SDRAMs) or two SDRAMs (8 BGAs). External trace lengths should be minimized. All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer.
Page 153: Cpc Signal Topology
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration 7.3.7.1. CPC Signal Topology Figure 72. Command Per Clock Signal Routing Topology 4 Load BGA Figure 73. CPC Signal Routing Topology 4 Load TSOP ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 154: Figure 74. Cpc Signal Routing 8 Load Bga Topology
The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals. CPC signals should be routed on inner layers with minimized external trace lengths. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 155: Cpc Signal Routing Guidelines
Count Per Signal CPC to SCK/SCK# [5:0] Length Matching Requirements See length matching Section 7.3.7.3 and Figure 76 for details. NOTES: 1. Variance per topology for TL1, TL2, and TL3 + 10 mils. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 156: Cpc To Clock Length Matching Requirements
CPC signals and clock. A nominal CPC package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 157: Cpc Group Package Length Table
Table 56. CPC Group Package Lengths Signal Pin Number Pkg Length (mils) SMAA_01 AD14 SMAA_02 AD13 SMAA_04 AD11 SMAA_05 AC13 SMAB_01 AD16 SMAB_02 AC12 SMAB_04 AF11 SMAB_05 AD10 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 158 System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 159: Integrated Graphics Display Port
The VESA video standard defines the LSB current for each DAC channel. The RAMDAC reference current is designed on-die to be equal to 32LSB. Therefore, the external reference resistor value is defined as: ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 160: Ramdac Board Design Guidelines
R, G, B signal be routed single-endedly. The analog RGB signals should be routed with an impedance of 37.5 Ω. Intel recommends that these routes be routed on an inner routing layer and that it be shielded with VSS planes, if possible. Spacing between DAC channels and to other signals should be maximized;...
Page 161: Ramdac Routing Guidelines
The DAC channel (red, green, blue) outputs should be routed as single-ended shielded routes to an analog switch to support a docking station. An analog switch should be used in order to provide the proper termination that is required for high-performance video signal integrity. See Figure 79. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 162: Table 57. Recommended Gmch Dac Components
Ron < 8 Ω , Con < 10 pF Analog ------- ------- Rated for a continuous Switch channel current of Texas Instruments SN74CB3Q3306 100mA (min) NOTE: Not needed when using 855GME platform with external graphics only. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 163: Dac Power Requirements
Designs should provide as clean and quiet a supply as possible to the VCCA_DAC. Additional filtering and/or separate voltage rail may be needed to do so. On the Intel CRB, there is a placeholder for a LC filter in case there is noise present in the VCCA power rail.
Page 164: Hsync And Vsync Design Considerations
3.3-V outputs from the GMCH. Some monitors have been found to drive HSYNC and VSYNC signals during reset. Because these signals are used as straps on the 852GM/GME and 855GM/GME chipsets, the GMCH can enter an illegal state under these conditions. In order to prevent these signals from being driven to the GMCH during reset, system designers must ensure the GMCH is isolated from any monitor driving HSYNC or VSYNC while PCI_RST# is active.
Page 165: Lvds Length Matching Constraints
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 166: Table 59. Lvds Signal Group Routing Guidelines
LVDS Transmitter signals. • Traces must be ground referenced and must not switch layers between the GMCH and connector. When choosing cables, it is important to remember: ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 167: Table 60. Lvds Package Lengths
399.6 IYBP0 359.8 IYAM0 385.4 IYBM0 353.7 CHANNEL IYAP1 487.5 CHANNEL IYBP1 524.7 IYAM1 466.2 IYBM1 516.6 IYAP2 572.6 IYBP2 623.3 IYAM2 566.2 IYBM2 604.2 IYAP3 643.2 IYBP3 441.8 IYAM3 637.8 IYBM3 441.7 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 168: Digital Video Out Port
TMDS transmitter or integrated TV encoder and TMDS transmitter). The GMCH has two dedicated Digital Video Out Ports, DVOB and DVOC. Intel’s DVO port is a 1.5-V only interface that can support transactions up to 165 MHz. Some of the DVO port command signals may require voltage translation circuit depending on the third party device.
Page 169: Package Length Compensation
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation.
Page 170: Table 63. Dvob And Dvoc Routing Guideline Summary
4 mils and a trace spacing of 7 mils. The signals should be separated to a trace width of 4 mils and a trace spacing of 8 mils within 0.3 inches of the GMCH component. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 171: Dvob And Dvoc Assumptions, Definitions, And Specifications
The flight time skew simulations simulate all parameters that could cause a skew between two signals, including motherboard and add-in card line lengths, effective capacitance in the buffer models, crosstalk on each of the different interconnect combinations, data pattern dependencies, and ISI induced skews. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 172: Dvob And Dvoc Simulation Method
Units Driver Data Valid before Strobe tDVb Data Valid after Strobe tDVa Interconnect Allowable Skew Vendor specific Vendor specific Receiver Data Setup to Strobe tDSu Vendor specific Data Hold from Strobe Vendor specific ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 173: Dvob And Dvoc Port Flexible (Modular) Design
Figure 83 shows the generic connector model used in simulation for flexible DVO implementation. This is only for reference. Actual connector may have different parasitic values. Designs using this approach need to be simulated first. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 174: Dvo Gmbus And Ddc Interface Considerations
If any of GMBUS pairs are not used, 2.2 k – 100 kΩ pull-up (or pull-ups with the appropriate value derived from simulating the signal) resistors are required, except for CRT DDCADATA/DDCCLK and ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 175: Leaving The Gmch Dvob Or Dvoc Port Unconnected
Integrated Graphics Display Port LCLKCTRLA/LCLKCTRLB GMBUS pair. LCLKCTRLA/LCLKCTRLB are used as bootup straps. Please refer to the Intel 855GM/GME (Montara-GM/GM+) Chipset GMCH External Design Specification for details on strapping option. This will prevent the GMCH from confusing noise on these lines for false cycles.
Page 176: Figure 84. Gvref Reference Voltage
Integrated Graphics Display Port Figure 84. GVREF Reference Voltage +V1.5S 1 KΩ 1% GVREF (to DVO device) GVREF(to GMCH) 0.1 µF 0.1 µF 1 KΩ 1% ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 177: Agp Port Design Guidelines
SERR#/PERR# are not supported. AGP 4X, 2X, and 1X operate at 1.5 V only. AGP semantic cycles to DRAM are not snooped on the host bus. The Intel 855GME GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization.
Page 178: Table 68. Agp 2.0 Signal Groups
SB_STB SB_STB, SB_STB# data is sampled on rising clock edges. The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals) will be addressed separately. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 179: Agp Routing Guidelines
AGP 1X timing domain signals (refer to Table 68) can be routed with 4-mil minimum trace separation. 9.2.1.3. Trace Length Mismatch There are no trace length mismatch requirements for 1X timing domain signals. These signals must meet minimum and maximum trace length requirements. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 180: 2X/4X Timing Domain Routing Guidelines
4-mil traces with 8 mils of space (1:2) between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 15 mils (1:3). ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 181: Trace Length Mismatch Requirements
The strobe pair must be length matched to less than ± 0.01 inches (that is, a strobe and its compliment must be the same length within ± 0.01 inches). Table 73 shows the AGP 2.0 routing summary. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 182: Agp Clock Skew
These should be placed within 70 mils of the outer row of balls on GMCH for VDDQ decoupling. Ideally, this should be as close as possible. • Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 body- type X7R dielectric.
Page 183: Agp Interface Package Lengths
GCBEB_0 GAD16 GCBEB_1 GAD17 GCBEB_2 GAD18 GCBEB_3 GAD19 GST_0 GAD20 GST_1 GAD21 GST_2 GAD22 GRBFB GAD23 GWBFB GAD24 GFRAMEB GAD25 GIRDYB GAD26 GTRDYB GAD27 GSTOPB GAD28 GDEVSELB GAD29 GREQB GAD30 GGNTB GAD31 GPAR ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 184: Agp Routing Ground Reference
9.2.6. AGP Routing Ground Reference Intel strongly recommends that at least the following critical signals be referenced to ground from the GMCH to an AGP controller connector using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and ST[2:0].
Page 185: Table 75. Agp Pull-Up/Pull-Down Requirements And Straps
Pull-Up NOTES: 1. The Intel 855GME chipset GMCH has integrated pull-ups to ensure that these signals do not float when there is no add-in card in the connector. 2. The Intel 855GME chipset GMCH does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are required for AGP graphics controllers that implement these signals.
Page 186: Agp Vddq And Vcc
9.2.10. AGP Compensation The Intel 855GME chipset GMCH AGP interface supports resistive buffer compensation. For Printed Circuit Boards with characteristics impedance of 55 Ω, connect the GRCOMP pin to a 40.2 Ω ± 1% pull-down resistor (to ground) via a 10-mil wide, very short (≈ 0.5 inches) trace.
Page 187: Hub Interface
This hub interface connects the ICH4-M to the GMCH. The ICH4-M should strap its HLRCOMP pin to V =1.5 V, as summarized in Table 77. The 855GM chipset GMCH should strap its HLRCOMP pin to V =1.2 V, the 855GME chipset GMCH should strap its HLRCOMP pin to =1.35 V as summarized in Table 77.
Page 188: Hub Interface Data Hl[10:0] And Strobe Signals
(inch) (inch) length signals (mils) (mils) HL[10:0] 1.5” 6” ± 100 Differential HLSTB pair HLSTB 1.5” 6” ± 100 Data lines HLSTB and HLSTB# must HLSTB# be ± 10 mils of each other ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 189: Table 79. Hub Interface Package Lengths For Ich4-M
HUB_PD10 HUB_PD11 HUB_CLK HUB_PSTRB HUB_PSTRB# Table 80. Hub Interface Package Lengths for GMCH Signal Pin Number Package Length (mils) HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] GCLKIN HLSTB HLSTB# ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 190: Terminating Hl[11]
GMCH and ICH4-M. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). If the trace length exceeds 4 inches then the locally generated voltage reference divider should be used. See section 10.3.2 for the more details. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 191: Locally Generated Voltage Reference Divider Circuit
1% tolerance (see Table 82). Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). If the voltage specifications are not met then individually generated voltage divider circuit for HIVREF and HI_VSWING is required. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 192: Single Gmch And Ich4-M Voltage Generation / Separate Divider Circuit For Vswing/Vref
C2, C5 = 0.01 µF (near component) R6 = 78.7 Ω ± 1% HI_VSWING VCCHI=1.5 V C1 = 0.1 µF (near divider) (800mV) R7 = 24.2 Ω ± 1%, C4, C6 = 0.01 µF (near component) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 193: Separate Gmch And Ich4-M Voltage Generation / Separate Divider Circuits For Vref And Vswing
ICH4-M and GMCH. The reference voltage for both HIVREF and HI_VSWING must meet the voltage specification in Table 81. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). Note that resistor values used for 855GM chipset GMCH and 855GME chipset GMCH are different since Vcc GMCH is different.
Page 194 Hub Interface This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 195: I/O Subsystem
11.1. IDE Interface This section contains guidelines for connecting and routing the Intel 82801DBM ICH4-M IDE interface. The ICH4-M has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
Page 196: Primary Ide Connector Requirements
• The 10-kΩ resistor to ground on the PDIAG#/CBLID# signal is required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 197: Secondary Ide Connector Requirements
• The 10-kΩ resistor to ground on the PDIAG#/CBLID# signal is required on the Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 198: Mobile Ide Swap Bay Support
IDE channels, respectively. By default, these bits are set to 0 and during normal power up, should be set to 1 by the BIOS to enable IORDY assertion from the IDE device when an access is requested. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 199: S5/G3 To S0 Boot Up Procedures For Ide Swap Bay
IDE device once again and waits for the assertion of IORDY in response to an access request. 3. Once the system IDE interface is configured for normal operation once again, the reset signal to the swap device should be de-asserted to allow the drive to initialize. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 200: Pci
I/O Subsystem 11.2. The Intel 82801DBM ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high performance data streaming when the ICH4-M is acting as either the target or the initiator in the PCI bus.
Page 201: Figure 95. Intel 82801Dbm Ich4-M Ac'97 - Codec Connection
NOTE: If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the Intel ICH4-M Datasheet. Clocking is provided from the primary codec on the link via AC_BIT_CLK, and is derived from a 24.576-MHz crystal or oscillator.
Page 202: Figure 96. Intel 82801Dbm Ich4-M Ac'97 - Ac_Bit_Clk Topology
I/O Subsystem AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that there is at least one codec. Figure 96. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ® Intel ICH4 AC_BIT_CLK Primary Codec Table 85.
Page 203: Figure 98. Intel 82801Dbm Ac'97 - Ac_Sdin Topology
CS4205b codec was used a 47- Ω resistor for R1 was best. 2. Bench data shows that a 47- Ω resistor for R1 is best for the Sigmatel* 9750 codec. Figure 98. Intel 82801DBM AC’97 – AC_SDIN Topology Codec ®...
Page 204: Ac'97 Routing
Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. • Locate the crystal or oscillator close to the codec. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 205: Motherboard Implementation
(R ), and the ICH4-M’s integrated pull-down resistor will be read as logic high (0.5 * VCC3_3 to VCC3_3 + 0.5 V). ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 206: Usb 2.0 Guidelines And Recommendations
Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 207: Usb 2.0 Trace Separation
The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6 Ω ±1% resistor to ground. Place the resistor within 500 mils of the ICH4-M and avoid routing next to clock pins. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 208: Usb 2.0 Termination
2. All lengths are based upon using a common-mode choke (see Section 11.4.4.1 for details on common-mode choke). 11.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch) The following guidelines apply to the use of plane splits voids and cutouts. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 209: Vcc Plane Splits, Voids, And Cut-Outs (Anti-Etch)
If the system fuse is rated at 1amps then the power carrying traces should be wide enough to carry at least 1.5 amps. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 210: Emi Considerations
Common mode chokes with a target impedance of 80 Ω to 90 Ω at 100 MHz generally provide adequate noise attenuation. Finding a common mode choke that meets the designer’s needs is a two-step process. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 211: Esd
Therefore, the system designers should ensure that, on their particular system implementation, there is enough current supplied to the Bluetooth device during suspend state in order for selective suspend to function properly. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 212: I/O Apic (I/O Advanced Programmable Interrupt Controller)
APIC bus or FSB. Furthermore, on Intel Pentium M processor / Intel Celeron M based systems, the ICH4-M has the option to let the integrated I/O APIC behave as an I/O (x) APIC. This allows the ICH4-M to deliver interrupts in a parallel manner rather than just a serial one.
Page 213: Figure 104. Smbus 2.0/Smlink Protocol
ASIC (such as Intel 82562EM 10/100 Mbps Platform LAN Connect) to access targets on the SMBus as well as the ICH4-M Slave Interface. Additionally, the ICH4-M supports slave functionality, including the Host Notify protocol, on the SMLink pins.
Page 214: Smbus Architecture And Design Considerations
2. The maximum bus capacitance that a physical segment can reach is 400 pF. 3. The Intel ICH4-M does not run SMBus cycles while in S3. 4. SMBus devices that can operate in S3 must be powered by the V supply.
Page 215: Calculating The Physical Segment Pull-Up Resistor
4.7 k Ω to 1.2 k Ω 100 to 200 pF 3.3 k Ω to 1.2 k Ω 200 to 300 pF 2.2 k Ω to 1.2 k Ω 300 to 400 pF ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 216: Fwh
ICH4-M FWH signal INIT#. Trace lengths and resistor values can be found in Table 16. The Voltage Translator circuitry is shown in Figure 16. It is strongly recommended that any system that implements a FWH should have its INIT# input connected to the ICH4-M. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 217: Fwh Vpp Design Guidelines
Due to the large routing solution space and necessity of a voltage translator in the design of a FWH on Intel Pentium M processor / Intel Celeron M processor and ICH4-M based platforms, the following timing requirements must be met to ensure proper system operation.
Page 218: Rtc
I/O Subsystem 11.8. The Intel 82801DBM ICH4-M contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down.
Page 219: Rtc Crystal
I/O Subsystem 11.8.1. RTC Crystal The Intel 82801DBM ICH4-M RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 109 documents the external circuitry that comprises the oscillator of the ICH4-M RTC.
Page 220: External Capacitors
(+23 ppm) but this configuration of C makes the circuit oscillate ° closer to 32.768 kHz at 0 C. The 6.8 pF value of C1 and 2 is the practical value. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 221: Rtc Layout Considerations
To do this, the diodes are set to be reverse biased when the system power is not available. Figure 110 is an example of a diode circuit that is used. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 222: Rtc External Rtcrst# Circuit
The RC time delay should be in the range of 18 ms - 25 ms. Any resistor and capacitor combination that yields the proper time constant is acceptable. When RTCRST# is asserted, bit 2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1, and ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 223: Susclk
11.9. Internal LAN Layout Guidelines The Intel 82801DBM ICH4-M provides several options for LAN capability. The platform supports several components depending upon the target market. Available LAN components include the Intel ®...
Page 224: Footprint Compatibility
11.9.1. Footprint Compatibility The Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Fast Ethernet Controller are all manufactured in a footprint compatible 15 mm x 15 mm (1-mm pitch), 196-ball grid array package. Many of the critical signal pin locations on the 82540EM and the 82551QM are identical, allowing designers to create a single design that accommodates any one of these parts.
Page 225: Intel ® 82801Dbm Ich4-M - Lan Connect Interface Guidelines
• LAN_CLK • LAN_RSTSYNC • LAN_RXD[2:0] • LAN_TXD[2:0] This interface supports Intel 82562ET and Intel 82562EM components. Signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0] are shared by all components. The AC ® characteristics for this interface are found in the Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4- M) Specification Update.
Page 226: Bus Topologies
• Direct point-to-point connection between the ICH4-M and the LAN component • LOM Implementation 11.9.2.1.1. LAN On Motherboard Point-To-Point Interconnect The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET is uniquely installed. Figure 113. Single Solution Interconnect...
Page 227: Crosstalk Consideration
11.9.3. Intel 82562ET / Intel 82562 EM Guidelines For correct LAN performance, designers must follow the general guidelines outlined in Section 11.9.6. Additional guidelines for implementing an Intel 82562ET or Intel 82562EM Platform LAN Connect component are provided below. ®...
Page 228: Guidelines For Intel 82562Et / Intel 82562Em Component
For a noise free and stable operation, place the crystal and associated discrete components as close as possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any noisy signals in this area.
Page 229: Critical Dimensions
If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector, distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as short as possible should be a priority.
Page 230: Magnetics Module (Distance B)
11.9.3.5.2. Termination Plane Capacitance Intel recommends that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing.
Page 231: Intel 82562Et/Em Disable Guidelines
10K 5% Intel® 82562EM/ET Disable 10K 5% There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for this design. ®...
Page 232: Design And Layout Consideration For Intel 82540Ep / 82551Qm
11.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM For specific design and layout considerations for the Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Faster Ethernet Controller, please refer to the following documents: • 82551QM / 82540EM Interchangeable LOM Design Application Note (AP 432) (Reference #10565) •...
Page 233: Figure 119. Trace Routing
And as a general rule, place traces from clocks and drives at a minimum distance from apertures by a distance that is greater than the largest aperture dimension. Figure 119. Trace Routing Trace Routing ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 234: 11.9.6.1.1. Trace Geometry And Length
To properly implement the common mode choke functionality of the magnetics module the chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 235: Figure 120. Ground Plane Separation
There should not be a power plane under the magnetics module. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 236: Common Physical Layout Issues
10. Use of capacitor that is too large between the transmit traces and/or too much capacitance from the magnetics' transmit center-tap (on the Intel 82562ET side of the magnetics) to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time so much that they fail the IEEE rise time and fall time specs.
Page 237: Power Management Interface
If an Intel Pentium M / Intel Celeron M processor ITP700FLEX debug port is implemented on the system, it is recommended that the DBR# signal of the ITP interface be connected to SYS_RESET# as well.
Page 238: Cpu I/O Signal Considerations
The Intel 82801DBM ICH4-Mhas been designed to be voltage compatible with the CMOS signals of the Intel Pentium M / Intel Celeron M processor. For Intel Pentium M / Intel Celeron M processor -based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the V rails for the processor the GMCH.
Page 239: Platform Clock Routing Guidelines
Table 98 below provides a breakdown of the various individual clocks. Note: When used in an Intel 855GM/GME chipset based system, the CK408 is configured in the unbuffered mode and has a host clock swing of 710 mV.
Page 240: Clock Group Topologies And Routing Constraints
These topologies and rules have been simulated and verified to produce the required waveform integrity and timing characteristics for reliable platform operation. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 241: Host Clock Group
The MULT0 pin (CK408 pin #43) should be pulled-up through a 10 kΩ to VCC – setting the multiplication factor to 6. The IREF pin (CK408 pin #42) should be tied to ground through a 475 Ω ± 1 % resistor – making the IREF 2.32 mA. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 242: Table 99. Host Clock Group Routing Constraints
2. To minimize skew it is recommended that all clocks be routed on a single layer. If clock pairs are to be routed on multiple layers, the routed length on each layer should be equalized across all clock pairs. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 243: Host Clock Group General Routing Guidelines
Once routing lengths are defined for the CPU and GMCH, match the motherboard length of the ITP clock pair to the motherboard length of the CPU clock pair. Table 100. Clock Package Length Parameter Length Intel Pentium M Processor / Intel Celeron M Processor 485 mils Package Length Intel 855GM/GME Chipset GMCH Package Length 1142 mils...
Page 244: Emi Constraints
Clocks are a significant contributor to EMI and should be treated with care. The following recommendations can aid in EMI reduction: • Maintain uniform spacing between the two halves of differential clocks. • Route clocks on physical layer adjacent to the VSS reference plane only. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 245: Clk66 Clock Group
These clocks are all length tuned to match each other and as well as to the CLK33 clocks. Figure 125. CLK66 Clock Group Topology CK408 GMCH ICH4-M ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 246: Table 101. Clk66 Clock Group Routing Constraints
HCLK going to the GMCH (BCLK) is recommended in order to prevent the CLK66 rising edge from occurring within the +/- 350ps keepout area on either side of the HCLK edge. See Section 12.2.1.3 for details. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 247: Clk33 Clock Group
Clock to Clock Matching +/- 100 mils CLK33 to CLK66 Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 248: Pci Clock Group
+/- 2.0” PCICLK to (CLK33 – 2.5”) Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 249: Clk14 Clock Group
Clock to Clock Length Matching +/- 500 mils CLK14A to CLK14B Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 250: Dotclk Clock Group
Care should be taken to avoid routing through noisy areas and spacing rules should be observed. Guard traces may be employed if necessary with ground stake vias on no less than 0.5- inch intervals. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 251: Sscclk Clock Group
Total Length Range – L1 + L2 + L3 + L4 3.0” to 8.5” Length Matching Required Breakout Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 252: Usbclk Clock Group
Total Length Range – L1 + L2 3.0” to 12.5” Length Matching Required Breakout Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 253: Clock Updates For Intel Pentium M Processor And Intel Celeron M Processor Platforms
CK-408 Clock Updates for Intel Pentium M Processor and Intel Celeron M Processor Platforms To maximize the power savings on 855GM chipset based systems, additional control registers have been added to the CK-408clock generator to allow option to tri-state the CPU[2:0] host clocks during CPU_STOP# or PWRDWN assertion.
Page 254 Platform Clock Routing Guidelines This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 255: Intel 855Gm/Gme Chipset Based System Power Delivery Guidelines
13.2. Platform Power Requirements The following figure shows the power delivery architecture for an example of the Intel 855GM/GME chipset based system. To ensure that enough power is available during S3, a thorough power budget should be completed. The power requirements should include each device’s power requirements, both in suspend and in Full-On.
Page 256: Platform Power Delivery Architectural Block Diagram
Intel 855GM/GME Chipset Based System Power Delivery Guidelines The solutions given in this document are only examples. There are many power distribution methods that achieve similar results. It is critical, when deviating from these examples, to consider the effect of the change.
Page 257: Voltage Supply
HIGH HIGH HIGH S3 (STR) HIGH HIGH S4 (STD) HIGH S5 (Soft Off) 13.3.2. Power Supply Rail Descriptions Table 110. Power Supply Rail Descriptions on Intel Reference Board Signal Names Voltage Current Tolerance Enable Description +V1_25 1.25 0.01 +/- 3.2%...
Page 258: 855Gm/Gme Chipset Based System Power-Up Sequence
However, good design practice would have all GMCH power rails come up as close in time as practical, with the core voltage (1.2 V for 855GM / 1.35 V for 855GME) coming up first. RSTIN#, which brings GMCH out of reset, should be deasserted only after PWROK has been active for 1 ms.
Page 259: Ich4-M Power Sequencing Requirements
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Figure 133. GMCH Power-Up Sequence CPURST# 1ms max RSTIN# 1ms min PWROK GMCH PWR Rails 13.4.3. ICH4-M Power Sequencing Requirements The following figure describes the power-on timing sequence for ICH4-M. The VGATE input should be connected to the processor voltage regulator PWRGD output.
Page 260: Figure 134. Ich4-M Power-Up Sequence
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Figure 134. ICH4-M Power-Up Sequence System S0 state State Hub interface "CPU Reset Complete” Message STPCLK#, STP_CPU#, STP_PCI# SLP_S1#, C3_STAT# T186 T184 Frequency Strap Values Normal Operation Straps T185 PCIRST# T178 T181...
Page 261: 1.5 V Power Sequencing
V , or before 5REF within 0.7 V. These rules must be followed in order to ensure proper functionality of the Intel ICH4-M. Figure 135 shows a sample implementation of how to satisfy the V / 3.3 V sequencing rule.
Page 262: Design Guidelines
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Figure 135. Example V Sequencing Circuitry 5REF 5REFSUS 13.4.3.3. Design Guidelines 5REFSUS The aforementioned rule for V also applies to the V input pin. However, in some platforms, 5REF 5REF the V...
Page 263: Ddr Memory Power Sequencing Requirements
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Figure 137. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option +V5S or +V5 Customer specific or Customer specific or +V3ALWAYS Intel recommended Intel recommended USB power circuit USB power circuit V5REF_SUS2...
Page 264: Intel 855Gm/Gme Chipset Based System Power Delivery Guidelines
Intel recommends that the developer use the amount of decoupling capacitors specified in this document to ensure the component maintains stable supply voltages. The capacitors should be placed as close to the package as possible.
Page 265: 855Gm/Gme Chipset Gmch Decoupling Guidelines
Intel 855GM/GME Chipset Based System Power Delivery Guidelines 13.5.1. 855GM/GME Chipset GMCH Decoupling Guidelines Decoupling in Table 15 is based on voltage regulator solution used on the customer reference board design. Table 113. GMCH Decoupling Recommendations Pin Name Configuration TYPE...
Page 266: Gmch Vccsm Decoupling
Intel 855GM/GME Chipset Based System Power Delivery Guidelines 13.5.1.1. GMCH VCCSM Decoupling For the VCCSM pins of the GMCH, a minimum of eleven, 0603 form factor, 0.1-µF, high frequency capacitors is required and must be placed within 150 mils of the GMCH package. The capacitors should be evenly distributed along the GMCH DDR system memory interface and must be placed perpendicular to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH.
Page 267: V Power Delivery Guidelines
Intel 855GM/GME Chipset Based System Power Delivery Guidelines • JEDEC Standard, JESD79 (release 2), Double Data Rate (DDR) SDRAM Specification • Intel DDR 266 JEDEC Spec Addendum Rev 1.0 or later Figure 139. DDR Power Delivery Block Diagram + V 5...
Page 268: Ddr Smrcomp Resistive Compensation
The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer ® characteristics to specific board and operation environment characteristics. Refer to the RS – Intel 855GM/GME (Montara-GM/GM+) Chipset GMCH External Design Specification and Figure 140 for details on resistive compensation. The SMRCOMP signal should be routed with as wide a trace as possible.
Page 269: Ddr Smrcomp And Vtt 1.25-V Supply Disable In S3/Suspend
Intel 855GM/GME Chipset Based System Power Delivery Guidelines tolerance and VTT can vary more easily depending on signal states. A solid 1.25V termination island should be used to for this purpose and be placed on the surface signal layer, just beyond the last SO- DIMM connector and must be at least 50 mils wide.
Page 270: Gmch Agtl+ I/O Buffer Compensation
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Figure 143. GMCH HAVREF Reference Voltage Generation Circuit +VCCP GMCH 49.9 GMCH_HAVREF HAVREF 0.1uF Figure 144. GMCH HCCVREF Reference Voltage Generation Circuit +VCCP GMCH 49.9 GMCH_HCCVREF HCCVREF 0.1uF 13.5.3.2. GMCH AGTL+ I/O Buffer Compensation The HXRCOMP and HYRCOMP pins of the GMCH should each be pulled-down to ground with a 27.4...
Page 271: Gmch Agtl+ Reference Voltage
Intel 855GM/GME Chipset Based System Power Delivery Guidelines 13.5.3.3. GMCH AGTL+ Reference Voltage The GMCH’s AGTL+ I/O buffer resistive compensation mechanism also requires the generation of reference voltages to the HXSWING and HYSWING pins with a value of 1/3*VCCP. Implementations for HXSWING and HYSWING voltage generation are illustrated in Figure 146.
Page 272: Ich4-M Decoupling / Power Delivery Guidelines
Intel recommends that the developer use the amount of high frequency decoupling capacitors specified in table below to ensure that component maintains stable supply voltages.
Page 273: Hub Interface Decoupling
Intel 855GM/GME Chipset Based System Power Delivery Guidelines Table 115. ICH4-M Decoupling Requirements Pin Name Configuration VCC3_3 Connect to Vcc3_3S 0.1 µF VCCSUS3_3 Connect to Vcc3_3A 0.1 µF VCCLAN3_3 Connect to Vcc3_3 0.1 µF V_CPU_IO Connect to Vccp IMVP-IV 1 µF 1 µF...
Page 274 Intel 855GM/GME Chipset Based System Power Delivery Guidelines This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 275: Intel Pro/Wireless 2100/2100A - Bluetooth Coexistence Interface Design Requirements
Design Requirements This section describes the design requirements needed to support the Intel PRO/Wireless 2100/2100A wireless component, a critical component of the latest Intel Centrino mobile technology. The following discussion provides guidelines on the interface design between the Intel PRO/Wireless 2100/2100A 802.11a/b wireless LAN device and the Bluetooth module of choice supporting the coexistence...
Page 276: Dc Power Requirements For Bluetooth
(estimated to be < 15 ms) the Bluetooth module’s GPIOs will default to either inputs or a high impedance state. Since the logic level of the Intel PRO/Wireless 2100/2100A coexistence signals is not known during this time, it is important that no logic “high”...
Page 277: Usb Selective Suspend
Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements This concern exists for any condition in which the power provided to either component has been disabled through any number of means. The solution illustrated in Figure 148 will adequately prevent any of these possible conditions from affecting system performance or damaging the hardware.
Page 278 Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements This page intentionally left blank. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 279: Reserved, Nc, And Test Signals
Processor RSVD Signals The Intel Pentium M processor and Intel Celeron M processor each have a total of three TEST, and eight RSVD signals that are Intel reserved in the pin-map. All other RSVD signals are to be left unconnected but should have access to open routing channels for possible future use.
Page 280: Intel 855Gm/Gme Chipset Gmch Rsvd Signals
Intel 855GM/GME Chipset GMCH RSVD Signals The Intel 855GM/GME chipset GMCH has a total of 13 RSVD and 12 NC signals that are Intel reserved in the pin-map. The recommendation is to provide test points for all RSVD signals for possible future use.
Page 281: Platform Design Checklist
The following checklist provides design recommendations and guidance for the Intel Pentium M processor and Intel Celeron M processor systems with the Intel 855GM/855GME chipset. It should be used to ensure that design recommendations in the design guide have been followed prior to schematic reviews.
Page 282: Customer Implementation Of Voltage Rails
16.3. Design Checklist Implementation The voltage rail designations in this Design Checklist are intended to be as general as possible. The following table describes the equivalent voltage rails in the Intel CRB Schematics. Checklist Rail Intel CRB Rail On S0-S1...
Page 283 VxALWAYS rail can be the SUS rail depending on implementation. Vcc1_25 is the 1.25 V VTT rail for DDR. For Pentium M processor / Celeron M processor, VCCA is 1.8V, used for PLL. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 284: Intel Pentium M Processor / Intel Celeron M Processor
Platform Design Checklist 16.4. Intel Pentium M Processor / Intel Celeron M Processor 16.4.1. Resistor Recommendations Pin Name System Series Voltage Notes Termination Translation Pull-up/Pull-down A20M# Point-to-point connection to ICH4-M. BR0# Point-to-point connection to GMCH. COMP0, 27.4 Ω ± 1% pull- Resistor placed within 0.5”...
Page 285 VCC[71:0] Connect to VccCORE VCCA[3:0] Connect to Vcc1_8 Connect to Vcc1_8 for Intel Pentium M processor. Connect to either Vcc1_8 or Vcc1_5 for Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache. VCCP[26:0]...
Page 286: Figure 149. Routing Illustration For Init
Figure 149. Routing Illustration for INIT# 3.3V V_IO_FWH 3.3V ICH4-M 3904 3904 Figure 150. Voltage Translation Circuit for PROCHOT# 3.3V 3.3V 330ohm +/-5% 1.3K To Receiver +/-5% 330ohm 3904 +/-5% From Driver 3904 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 287: In Target Probe (Itp)
2.5 nH / 12 (Polymer Covered Tantalum - POSCAP, Neocap, KO Cap) 10 x 0.1 µ F 16 m Ω (typ) / 10 High Frequency Decoupling 0.6 nH / 10 (0603 MLCC, >= X7R) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 288: Vcca (Pll)
X5R) NOTES: Decoupling guidelines are recommendations based on our reference board design. The Intel Customer Reference Board uses option #4. This is the preferable option to use. When deciding on overall decoupling solution, customers will need to take layout & PCB board design into consideration.
Page 289: Clock Checklist
Connect to a 14.318 MHz crystal, placed within 500 XTAL_OUT mils of CK-408 VDD[7:0], VDDA Connect to Vcc3_3 Refer to clock vendor datasheet for decoupling info. VSS[5:0], VSSA Connect to gnd VSSIREF Connect to gnd ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 290: Figure 151. Clock Power-Down Implementation
Platform Design Checklist Figure 151. Clock Power-down Implementation VccSus3_3 PM_SLP_S1# CLK_PWRDWN# PM_SLP_S3# ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 291: Intel 855Gm/855Gme Checklist
150 Ω 1% pull-up to VccSus2_5 Signal voltage level = 4/5 * VccSus2_5. Need 0.1 µF cap at pin. 604 Ω 1% pull-down to gnd This signal may be optionally connected to Vcc2_5 and powered off in S3. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 292 Signal voltage level = 1/2 * VccSus2_5. VccSus2_5 Need 0.1 µF cap by the voltage divider. 60.4 Ω 1% pull-down to gnd This signal may be optionally connected to Vcc2_5 and powered off in S3. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 293: Ddr So-Dimm Interface
0.01 µF is powered OFF. Vcc2_5Sus 0.1 µF A minimum of 9 high frequency caps are recommeneded to be placed bewteen the SO-DIMMS. A minimum of 4 low frequency caps are 100-150 µF required. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 294: Fsb
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF cap and one 1 µF cap for voltage divider. 100 Ω 1% pull-down to gnd Figure 153. GMCH HXSWING & HYSWING Reference Voltage Generation Circuit +VCCP +VCCP HXSWING HYSWING] HXSWING HYSWING GMCH ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 295: Hub Interface
“no connect.” YBP[3:0]/YBM[3:0] CLKAP/CLKAM If any of these LVDS clock pairs are not used, they can be left as “no connect.” CLKBP/CLKBM LVREFH, LVREFL, These signals should be left as NC. LVBG ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 296: Dvo
If DVO interface is used, leave as NC. This signal has internal pull-down. if DVO interface is unused DPMS Connect to 1.5-V version of ICH4-M’s SUSCLK or a clock that runs during S1. See Figure 154. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 297: Dac
33 pF cap to gnd VSYNC On VGA side of series resistor: 39 Ω Use to unidirectional buffer to prevent potential electrical overstress and illegal operation of the GMCH. 33 pF cap to gnd ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 298: Miscellaneous
Connect to the processor. AA22) LCLKCTLB Leave as NC if not used. LCLKCTLA Leave as NC if not used. GST[2:0] Leave as NC or 1 k Ω pull-up to Vcc1_5 These pins have internal pull-down. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 299: Gmch Decoupling Recommendations
This power signal may be optionally connected to Vcc2_5 47 µF and powered off in S3. VCCGPIO Connect to Vcc3_3 0.1 µF Bulk decoupling is based on VR solutions used on CRB design. 10 µF VCCAHPLL Connect to Vcc1_2 0.1 µF ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 300 GMCH side of inductor. 220 µF NOTE: Decoupling guidelines are recommendations based on our reference board design. Customers will need to take layout & PCB board design into consideration when deciding on overall decoupling solution. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 301: Ich4-M Checklist
INT_PIRQ#[A:D] External pull up is required for INT_PIRQ#[A:D]. INT_PIRQE#/GPIO2 External pull up is required when muxed signal INT_PIRQF#/GPIO3 (INT_PIRQ[E:H]#/ GPIO[2:5]) is implemented as INT_PIRQG#/GPIO4 PIRQ. INT_PIRQH#/GPIO5 INT_SERIRQ 8.2 k Ω pull-up to Vcc3_3 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 302: Gpio
• GPIO[34] can be used as SER_EN. • GPIO[35] can be used as FWH_WP#. • GPIO[36] can be used as FWH_TBL#. • GPIO[40] can be used as IDE_PATADET. • GPIO[41] can be used as IDE_SATADET. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 303: Agp_Busy# Design Requirement
This ICH4-M signal requires a pull-up to the switched 3.3-V rail (powered OFF during S3). Vcc3_3 This ICH4-M signal must be connected to the AGP_BUSY# output of GMCH. NOTE: Please also consult Intel for the latest AGP Busy and Stop signal implementation. 16.7.4. (SMBus) System Management Interface Pin Name...
Page 304: Ac '97 Interface
A series termination resistor is required for the PRIMARY CODEC. One series termination resistor is required for the SECONDARY/ TERTIARY CODEC connector card if the resistor is not found on the connector card. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 305: Ich4-M Power Management Interface
This signal to ICH4-M should not float. It needs to be at valid level all the time. if not actively driven. 16.7.7. FWH/LPC Interface Pin Name System Notes Pull-up/Pull-down LPC_AD[3:0] No extra pull-ups required. Connect straight to FWH/LPC. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 306: Usb Interface
HUB_VREF signal voltage level = 0.35 V ± 8%. HUB_VSWING 156. HUB_VSWING signal voltage level = 0.80 V ± 8%. Three options are available for generating these references. HUB_PD11 56 Ω pull-down to gnd ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 307: Figure 155. Single Or Locally Generated Gmch And Ich4-M Hivref/Hi_Vswing Circuit
R6 = 78.7 Ω ± 1%, R7 = 24.2 Ω ± 1% C1 and C3 = 0.1 µF PVSWING HI_VSWING (near divider) C2, C4, C5, C6 = Intel ® HLVREF HIREF 0.01µF (near GMCH ICH4 component) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 308: 16.7.10. Rtc Circuitry
VCCRTC powers the RTC well of the ICH4-M 3.3V Sus is Active Whenever System Plugged In RTCX1 is the Input to the Internal Oscillator Vbatt is Voltage Provided By Battery RTCX2 is the feedback for the external crystal ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 309: 16.7.11. Lan Interface
IDE_PDCS3#, IDE_PDDACK#, IDE_PDIOW#, IDE_PDIOR# IDE_PDDREQ These signals have integrated series resistors and pull-down resistors in ICH4-M. IDE_PIORDY 4.7 k Ω pull-up This signal has integrated series resistor in ICH4-M. to Vcc3_3 ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 310: 16.7.13. Secondary Ide Interface
(0.5 * Vcc3_3 to Vcc3_3 + 0.5) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 311: 16.7.15. Ich4-M Decoupling Recommendations
One 220 µF and two 470 pF are recommended for every two power lines. Either a thermister or a power distribution switch (with short circuit and thermal protection) is required. See Figure 158. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 312: Fwh Checklist
RST# 100 Ω ID[3:0] Signals are recommended to be connected to test points. RSVD[5:1] Signals are recommended to be connected to test points. NC[8:1] The signals should be left as NC (“Not Connected”) ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 313: Lan / Homepna Checklist
PM_PWROK to go high before deasserting this signal to enable the LAN device. It also keeps this signal high during S3. See Figure 159. Figure 159. LAN_RST# Design Recommendation VccSus3_3LAN 82562EM ISOL_TCK ISOL_TI ISOL_EX LAN_RST# ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 314: 16.10.2. Decoupling Recommendations
0.1 µF VCCP[2:1], VccSus3_3LAN 4.7 µF VCCA[2:1], VCCT[4:1] VCCR[2:1] Connect to 0.1 µF 4.7 uH from power supply to VCCR pins. VccSus3_3LAN via filter 4.7 µF Caps on VCCR side of the inductor. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 315: Schematics
Schematics Schematics Refer to the following page for schematics. ® Intel 855GM/855GME Chipset Platform Design Guide...
Page 316 PG 14 Backlight LVDS PG 15 GMCH Connector DDR SDRAM PG 16 PG 16 732 uFCBGA Intel 855GM: 200/266 MHz PG 46 Intel 855GME: 200/266/333 MHz PG 7,8,9,10 EVMC SLOT (CRT) PG 17 Hub Interface DDR VR PG 22 PG 22...
Page 317 Intel 855GM/GME CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION Voltage Rails I C / SMB Addresses Default Jumper Settings +VDC Primary DC system power supply (10 to 21V) Device Address Jumper Default Option Description Page Clock Generator 1101 001x...
Page 318 D51# H_D#20 H_D#52 AC22 18,37 H_SMI# CLK_CPU_BCLK 6 SMI# BCLK0 D20# D52# H_D#21 H_D#53 AC25 D21# D53# H_D#22 H_D#54 Intel Pentium M Processor AD23 D22# D54# H_D#23 H_D#55 AE22 D23# D55# H_D#24 H_D#56 AF23 D24# D56# H_D#25 H_D#57 AD24 D25#...
Page 319 AE14 VSS59 VSS156 VCC56 VCCSENSE AE16 VSS60 VSS157 VCC57 AE18 VSS61 VSS158 VCC58 VSSSENSE R2D2 AE20 VSS62 VSS159 Intel Pentium M Processor NO_STUFF_54.9_1% AE23 VSS63 VSS160 AE26 VSS64 VSS161 VSS65 VSS162 TP2D4 NO_STUFF_102276-100 VSS66 VSS163 VSS67 VSS164 AF11 VSS68 VSS165...
Page 320 GND5 ITP700-FLEXCON Note: C1F2 not needed for Customer Platforms Place TCK Title CPU Thermal Sensor & ITP pulldown resistor within 1" of ITP. Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 321 SCLK R2G5 SMB_CLK_S 8,11,12,16,18 SSC_SDATA R2G8 NO_STUFF_0 LCLKCTLB 7,8,16 SDATA R2G7 SMB_DATA_S 8,11,12,16,18 DREFSSCLK CLKOUT REF_OUT +V3.3S 5,8,9,11,15..18,20,21,23,26,31,33..36,38..40,45 DREFSSCLK_D R2G10 ICS91718 Title R2G12 CK-408 R2G11 Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 322 SMVREF SMVSWINGL RVSD6 TP_MCH_NC9 AJ19 AJ29 RSVD7 MCH_SMVSWINGH 10 SMVSWINGH RVSD7 TP_MCH_NC10 RSVD8 RVSD8 NC10 TP_MCH_NC11 C5F13 Intel 855GM/GME GMCH C5F6 C5F5 RSVD9 RVSD9 NC11 TP_RSVD10 RVSD10 0.1UF 0.1UF 0.1UF RSVD11 RVSD11 Intel 855GM/GME GMCH Title GMCH (1 of 3)
Page 323 HUB_PSTRB# H_RS#2 PSTRBF RS2# HUB_HLZCOMP HLZCOMP 0.1UF 0.1UF MCH_PSWING PSWING 10,46 MCH_HLVREF HLVREF Title C6T1 C6T2 Intel 855GM/GME GMCH GMCH (2 of 3) 0.1UF 0.1UF Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 324 VSS158 VCCGPIO_1 VCCASM0 R5R5 0.01_1% +V1.35S_GMCH_ASM AJ27 VSS74 VSS159 VCCASM1 AC28 C5D4 VSS75 VSS160 C5D2 C5R3 C5D17 C5D10 C6E14 Intel 855GM/GME GMCH AE28 VSS76 VSS161 C6E13 VSS77 VSS162 0.1UF 0.1UF 0.1UF 47uF 22UF 0.1UF 100uF VSS78 VSS163 AB15 VSS79 VSS164...
Page 325 9,44 +V2.5_GMCH_SM R6T9 NO_STUFF_56.2_1% System Memory C6T5 R6T8 R6T13 8,46 MCH_HLVREF 0.1UF 100_1% Title 60.4_1% GMCH Circuitry R6T11 C6T4 R6T10 MCH_SMRCOMP MCH_GTLREF3 60.4_1% Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> NO_STUFF_0 NO_STUFF_0.01UF Date: Monday, September 15, 2003 Sheet...
Page 326 M_DQS_R7 M_DATA_R_63 DQS7 DQ63 M_DQS_R8 DQS8 SO-DIMM 0 Layout note: Place capacitors between and near DDR connector if possible. Title DDR SO-DIMMs (1 of 2) Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 327 Layout note: Place capacitors between and near DDR connectors if possible. SO-DIMM 1 is placed farther from the GMCH than SO-DIMM 0 Title DDR SO-DIMMs (2 of 2) Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 328 M_CAS_FR# 11 M_DM7 M_DM_R_7 RP5G8D RP4G2C 7,12,14 M_RAS# M_RAS_FR# 11 M_DM8 M_DM_R_8 RP5G8B RP5G5C 7,12,14 M_WE# M_WE_FR# 11 M_DM_R_[8:0] 11,12,14 Title DDR Series Termination Size Project: Document Number 4.401 Custom Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 329 C5W12 C5W30 C4W5 C5W38 C5W16 C4W4 C6H3 C6H5 C5W8 C5W9 DDR Parallel Termination 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 330 GND9 ADD_RSVD_A10 GND10 ADD_RSVD_B11 GND11 GND12 DPMS_CLK PIPE# GND13 GND14 18,22,23,37 PCI_PME# PME# GND15 GND16 Title AGP Digital Display (ADD) Connector USB- GND17 USB+ GND18 Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 331 J5B1 100K R5N2 NO_STUFF_0 LCLKCTLB 6..8 No Stuff LVDS_BRIGHTNESS LVDS_BKLTEN SMB_CLK_D R5N9 6,8,11,12,18 SMB_CLK_S LCLKCTLA R5B2 R5N10 NO_STUFF_0 No Stuff INVERTER CONN 100K Title LVDS Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 332 DAC_QPCIEN DOCK_GREEN 25 DAC_HSYNC OE2# SPDT NO_STUFF_3.3pF DOCK_Q_HSYNC NO_STUFF_3.3pF C7B2 DAC_Q_HSYNC DAC_HSYNC C6B4 SN74LVC2G125 DOCK_VSYNC 25 R6N1 NO_STUFF_3.3pF Title DAC (CRT) Connector C6N6 NO_STUFF_3.3pF C6B5 Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 333 R6G4 74CBT3306 INT_APICD0 R6G2 INT_APICD1 C8G2 U8G1 R6W2 R6W8 R6W5 0.1UF Title 22..24,26,31,32,34,37 BUF_PCI_RST# ICH4-M (1 of 3) 74AHC1G08 Size Project: Document Number Buffer to reduce loading on PCI_RST# 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 334 C7Y1 10pF RTC_X2 Y7J1 PM_SUS_CLK 15,37 32.768KHZ R7J1 Title ICH4-M (2 of 3) Value for C7Y1, C7J4 depends on Xtal Q8H1 SUS_CLK BSS138 Size Project: Document Number <Doc> 4.401 Intel 855GM/GME CRB C7J4 10pF Date: Monday, September 15, 2003 Sheet...
Page 335 C8J3 20k_1% U7G2D ICH4-M R8J8 R8J10 Q8J3 BSS138 POK_DQ Q8J2 V1.5_PWRGD BSS138 R8J5 POK_D CR8J1A CR8J1B 3904 3904 PM_SLP_S4# 19,32,37,38,44,45 Title ICH4-M (3 of 3) Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 336 C4C3 and C4B8 near C4C6 near U4C1 Pin 9 Q4C1A. R4C1 R4C7 GND_V5A FAB ID Strapping Table ICH_FAB_REV BOARD FAB Title ICH4-M Pullups and Testpoints Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 337 PCI_REQA# 18,23 LEGACY HEADER NO_STUFF_0 INT_SERIRQ 18,23,24,32,34,37 FOR ADD-IN 5Pin_Keyed-HDR AUDIO CARD R7V1 TESTING 8.2K VIA SLOT1 ONLY Title PCI Slot 1 & 2 +V3.3S_ICH 19..21,24,37 Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Date: Monday, September 15, 2003 Sheet...
Page 338 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF PCI Slot3 is farthest Title PCI Slot 3/Moon-ISA support & Decoupling from processor Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 339 DOCK_CLKRUN# 25 PCI_GNT4# 18,21 PCI_REQ4# CLK_DOCKPCI DOCK_GNT4# 25 32,36,37 DOCK_INTR# DOCK_REQ4# 25 CLK_DOCKCONNPCI DOCK_DOCKINTR# 25 1OE# 2OE# Title R9C1 SN74CBTD3384 Docking Q-Switches QUIET DOCK Size Project: Document Number QSWITCH 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 340 UNDKRQ# V_ACDC3 CD4#/GND CD1# 200Pin_Docking-Plug 200Pin_Docking-Plug CR9C1 DOCK_SUSTAT# 19,32,37,38,44,45 PM_SLP_S3# 8,15..18,20,23,24,27,33..35,38..40,45,46 +V5S There is pull-up on BAR43 docking station. R9E1 17,24 DOCK_QPCIEN# Title Docking Connector Size Project: Document Number 4.401 <Doc> Intel 855GM/GME CRB Date: Monday, September 15, 2003 Sheet...
Page 341 IDE_SDDREQ 4.7K IDE_SDIOW# R3J1 IDE_SDIOR# IDE_SD_CSEL IDE_SIORDY IDE_SDDACK# 18,21,37 INT_IRQ15 IDE_SDA1 IDE_SATADET 19,37 IDE_SDA0 R2J1 IDE_SDCS1# IDE_SDACTIVE# 20x2-HDR IDE_SDCS3# IDE_SDA2 Title IDE 1 of 2 Size Project: Document Number Intel 855GM/GME CRB 4.401 <Doc> Date: Monday, September 15, 2003 Sheet...
Page 342 Place R9F3, R9F7 and R9G2 R2J3 0.1 to 0.4 inches from MDC header based on topology IDE_SDACTIVE#_Q IDE_SDACTIVE# DS2J1 Title GREEN IDE 2 of 2 / MDC INTERPOSER Size Project: Document Number Intel 855GM/GME CRB 4.401 <Doc> Monday, September 15, 2003 Date: Sheet...
Page 343 RP4B1D USB_OC2# 19 R4B1 U4B1 FB4B3 50OHM OC1# USBPWR_CONNE USBE_VCC OUT1 Title OUT2 USB (1 of 2) EN_U10 OC2# C4A7 OC2# C4A8 Size Project: Document Number 150UF TPS2052 470PF 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 344 470PF 150UF STACKED_RJ45_USB Clamping-Diode Clamping-Diode L5M1 USBB- USB_PN4 USBB+ USB_PP4 90@100MHz CR5M1 CR5M2 Clamping-Diode 5,15,19..23,27,28,32,36..39,45 +V3.3ALWAYS Clamping-Diode R7V10 USB_OC5# Title USB Connector (2 of 2) Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 345 PM_LANPWROK R6M1 Chassis GND Y5A1 (should cover part 82562EM of magnetics) 25MHZ C6A9 C6A8 J6A1 22PF 22PF NO_STUFF 82562EM Testpoint Header Title LAN Interface (82562EM) Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 346 TP_FWH_NC3 RSVD4 TP_FWH_RSVD3 TP_FWH_NC4 RSVD3 TP_FWH_NC5 RP9B1B TP_FWH_NC6 GND2 TP_FWH_NC7 GND1 TP_FWH_NC8 GNDA FWH SKT FWH sits in the Title FWH_TSOP_Socket, Size Project: Document Number Not on the board Intel 855GM/GME CRB 4.401 <Doc> Date: Monday, September 15, 2003 Sheet...
Page 347 System Management and Keyboard Controller KBC_A20GATE NMI_GATE# SMC_PROG_RST# SMC_MD Size Project: Document Number Note: for flash progamming, must use Intel 855GM/GME CRB CON3_HDR <Doc> 4.401 TX1 and RX1, which are pin97 and pin98. Date: Monday, September 15, 2003 Sheet CON14_RECEPT...
Page 348 0.1UF 2N3904 2N3904 2N3904 2N3904 Title LED_MUX_HI81 RP9H1A LED_MUX_HI81_D SMC Suspend Timer and Port 80 LEDs LED_MUX_HI80 LED_MUX_HI80_D RP9H1B LED_MUX_LO81 LED_MUX_LO81_D RP9H1C Size Project: Document Number LED_MUX_LO80 LED_MUX_LO80_D RP9H1D 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 349 0.1UF 22UF SIO_VR_VID5 40 EV_GPIO_0 EV_GPIO_1 DET_1.2V# R8U2 R8G4 R8G1 10K_1% NO_STUFF_470 NO_STUFF_470 Title Super I/O Controller 855GME core voltage detection Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Default: Pulled to GND Date: Monday, September 15, 2003 Sheet...
Page 350 R8M1 Floppy, Parallel, Serial, and IR Ports SER_RIA# is routed to allow the system to wake up in Suspend To RAM. Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Note: FORCEOFF# overrides FORCEON. Date: Monday, September 15, 2003 Sheet...
Page 351 PS/2 mouse. Otherwise, the keyboard PS/2 connector will only support a PS/2 keyboard. FB1A7 FB1A5 60ohm@100MHz 60ohm@100MHz MOUSE_CLK MOUSE_DATA CP1A1A CP1A1D 47PF 47PF Title Keyboard and Mouse Connectors Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 352 +V3.3 15,18..20,23,27,30,32,35,38,44,45 +V3.3_LPCSLOT R9G1 0.01_1% R9G5 0.01_1% Title C9G2 C9G1 C9G4 C8F1 C8F3 C9G3 LPC Slot & Debug Headers 22UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 353 DS2H2 GREEN LED for S3 DS1H2 LED for S5 DS2H1 GREEN GREEN Title Fan Circuit, Test Capacitors and System State LEDs Q2G3 BSS138 19,37 PM_SLP_S5# Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 354 MUX_SWITCH 74CBT16209A +VDC 16,21,45 20x2_Header 20x2_Header Title Processor VR Interposer Support & Power Circuitry Size Project: Document Number Connector 1 Connector 2 Intel 855GM/GME CRB <Doc> 4.401 VR Interposer Headers (rows A,B) (rows C,D) Date: Monday, September 15, 2003 Sheet...
Page 355 VR_VID_D4 VR_VID4 32,37 VR_ON SIO_VR_VID4 34 U1F1A LM339 VOUT_EVMC_B39 1.2V_EV R1F10 C2F5 0.1UF R1G1 VR_VID_D5 VR_VID5 SIO_VR_VID5 34 U1F1B LM339 Title IMVP-IV & Mux Buffer Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 356 Blank Title IMVP-IV VR Controller Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Date: Monday, September 15, 2003 Sheet...
Page 357 C3R14 C3R17 C3R18 C2R9 C2R6 C2R5 C2R7 C3R16 C2R8 C4D2 150UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF NO_STUFF_150UF Title Processor Decoupling Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Date: Monday, September 15, 2003 Sheet...
Page 358 Blank Title 855GME VR and VCCP Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Date: Monday, September 15, 2003 Sheet...
Page 359 R3G10 R3V9 C3V4 VSENSE_2_D C3H1 EV Support Resistor Options 267_1% 8200pF R3V10 NO_STUFF_0 19,20,32,37,38,45 PM_SLP_S4# 0.022uF Title R3V13 DDR VR NO_STUFF_4.99k_1% Vtt Sense Vtt Sense Size Project: Document Number 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 360 U1E2 C1E5 MASTER_RESET# 0.1UF PM_SYSRST# 19 74AHC1G08 3,5,46 ITP_DBRESET# CON72,RCPTL,TH,700000-668.Normal J1D1 20..23,27,36,37,44 +V5_TURNER R1D3 0.01_1% +V3.3 15,18..20,23,27,30,32,35,37,38,44 Title DC/DC Connector +V3.3_TURNER R1D5 0.01_1% Size Project: Document Number 3Pin_RECEPTICLE CON3,RCPTL,TH,700000-667.Normal 4.401 Intel 855GM/GME CRB <Doc> Date: Monday, September 15, 2003 Sheet...
Page 361 PG 39 PG 43 INTERPOSER_PRES# GMCH_VCORE_PWRGD PG 41 U4B3 ON_BOARD_VR_PWRGD U4B3 U4B3 PG 39 PG 39 INTERPOSER_PRES PG 39 U4B3 Title OFF_BOARD_VR_PWRGD Power On Check list Size Project: Document Number Intel 855GM/GME CRB 4.401 <Doc> Date: Monday, September 15, 2003 Sheet...
Page 362 SMC_RST# MAX809 U8A2 SMC_RES# PG 33 PG 32 PG 32 PG 31 SMC_PROG_RST# H_CPURST# GMCH PG 34 H_PWRGD PG 8 PG 3 Title Reset Map Size Project: Document Number Intel 855GM/GME CRB <Doc> 4.401 Date: Monday, September 15, 2003 Sheet...

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