Intel 855PM Design Manual page 335

A
42 MCH_RSVD2
10,11,12 M_A[12:0]
4
3
9 AGP_AD[31:0]
2
NOTE:
GRCOMP should be 10
mils wide and less then
0.5" from 855PM
1
A
B
M_DATA[63:0] 11
11 M_CB[7:0]
AGP
9 AGP_CBE#[3:0]
9 AGP_FRAME#
9 AGP_DEVSEL#
9 AGP_IRDY#
9 AGP_TRDY#
9 AGP_STOP#
9 AGP_PAR
R382
9 AGP_REQ#
40.2_1%
9 AGP_GNT#
GRCOMP
9 AGP_VREF
14 CLK_MCH66
9 AGP_ADSTB0
R382 use 36.5 Ohm for
9 AGP_ADSTB0#
55 Ohm board impedance
9 AGP_ADSTB1
9 AGP_ADSTB1#
AGP routing
9 AGP_SBA[7:0]
B
C
11 M_DQS[8:0]
MEMORY
HUB
9 AGP_SBSTB
9 AGP_SBSTB#
9 AGP_RBF#
9 AGP_WBF#
9 AGP_PIPE#
9 AGP_ST0
9 AGP_ST1
9 AGP_ST2
C
D
M_WE# 10,11,12
M_CAS# 10,11,12
M_RAS# 10,11,12
M_CLK_DDR0 10
M_CLK_DDR0# 10
M_CLK_DDR1 10
M_CLK_DDR1# 10
M_CLK_DDR2 10
M_CLK_DDR2# 10
C447
0.1UF
MEMORY
TP_U22_NC_0
TP_U22_NC_1
+V1.8S_MCH 7,8,42
R398
36.5_1%
M_CS3_R# 10,12
M_CS2_R# 10,12
M_CS1_R# 10,12,42
M_CS0_R# 10,12,42
M_BS1# 10,11,12
M_BS0# 10,11,12
M_CKE3_R 10,12
M_CKE2_R 10,12
M_CKE1_R 10,12,42
M_CKE0_R 10,12,42
MCH_TEST#
MCH_RSVD1 42
PCI_RST# 15,23,28,34,42
HUB_VREF_MCH 8
HUB_PSTRB# 8,15
HUB_PSTRB 8,15
HUB_PD[10:0]
Title
855PM MCH (1 of 3)
Size Project: Document Number
Custom 855PM Platform
Date: Monday, February 24, 2003 Sheet
D
E
4
M_CLK_DDR3 10
M_CLK_DDR3# 10
M_CLK_DDR4 10
M_CLK_DDR4# 10
M_CLK_DDR5 10
M_CLK_DDR5# 10
SM_VREF_MCH 40
C439
0.1UF
3
H_DPWR# 3
H_DPSLP# 3,15,34
Layout:
Provide Via on M_RCV#
2
for measurement
12,13,40,42 +V1.25S
R404 30.1_1%
C213
0.1UF
4,7,9,17,41 +V1.5S
R405
NO_STUFF_4.7K
1
8,15
Rev
6 of 4 7
E