Intel 855PM Design Manual page 128

System Memory Design Guidelines (DDR-SDRAM)
Pad to First SO-DIMM Pad
Trace Length L3 – First SO-DIMM Pad to Last
SO-DIMM Pad
Trace Length L4 – Last SO-DIMM Pad to Parallel
Termination Resistor Pad
Overall routing length from 855PM MCH to last
SO-DIMM Pad– L1+Rs+L2+L3 (required for
DDR333 support)
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via
Count Per Signal
Length Matching Requirements
NOTES:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
1.
Power distribution vias from Rt to Vtt are not included in this count.
2.
The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
3.
requirements.
It is possible to route using 4 vias if trace length L2 is routed on same external layer as SO-DIMM0 and a via is
4.
shared between SO-DIMM1 and parallel termination resistor.
L1 trace length does not include MCH-M package length and should not be used when calculating L1 length.
5.
Implementing a space to trace ratio of 3:1 (e.g. 12-mil space to 4-mil trace) for DQS[8:0] will produce a design
6.
with increased timing margins.
128
Max = 1.0"
Max = 0.80"
Min = 0.5"
Max= 4.5"
10 ± 5%
56 ± 5%
6
SDQ[71:0] to SDQS[8:0]
SDQS[8:0] to SCK/SCK#[5:0]
See Section 6.2.1for details
®
Intel 855PM Chipset Platform Design Guide
R
Figure 74 3
Figure 74
2, 4