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A
9,14,18,20,24,41
+V3.3_LPCSLOT
16
PM_SUS_CLK
4
9,16,17,18,19,20,24,25,26,29,33,36,41
+V3.3ALWAYS
15,29
H_RCIN#
29,33
KBC_A20GATE
16,29,31,33
SMC_EXTSMI#
+V5_LPCSLOT
16
LPC_DRQ#1
16,28,29,30,31
LPC_FRAME#
3
16,28,29,30,31
LPC_AD2
16,28,29,30,31
LPC_AD0
14
CLK_LPC14
R222
9,19,20,29
PCI_GATED_RST#
NO_STUFF_0
2
5,16,18,29
PM_THRM#
16,29
PM_PWRBTN#
29,41
SMC_ONOFF#
29,37
VR_ON
16,18,22,29,36
PM_PWROK
16,18,29
PM_RSMRST#
29,41
AC_PRESENT#
14,16,22,29,40,41
PM_SLP_S3#
29,41
SMC_SHUTDOWN
29
BAT_SUSPEND
29
SMC_RSTGATE#
21,29,33
DOCK_INTR#
1
17,18,19,20,24,40,41
+V5
R210
0.01_1%
A
B
+V12S
LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD
+V3.3_LPCSLOT
LPC Debug Slot
9,14,18,20,24,41
+V12S
J41
B1
A1
12V1
12V2
B2
A2
SUSCLK
NEG_12V
B3
A3
GND1
GND2
B4
A4
LREQ
BP_CLK
B5
A5
VCC3_1
VCC3_2
B6
A6
LCNTL0
LCNTL1
B7
A7
GND3
GND5
B8
A8
LDC
LD6
B9
A9
LD5
LD4
B10
A10
GND4
GND7
B11
A11
LD3
LD2
B12
A12
LD1
LD0
B13
A13
GND6
VCC5_2
B14
A14
3V_STBY
SCLK
B15
A15
LPS
GND10
B16
A16
KBRESTE#
SERIRQ
B17
A17
A20GATE#
CLKRUN#
B18
A18
GND8
GND12
B19
A19
LSMI#
LINK_ON
KEY
B20
A20
VCC5_1
VCC5_3
B21
A21
LDRQ1#
LDRQ0#
B22
A22
LFRAME1#
GND14
B23
A23
GND9
LAD3
B24
A24
LAD2
LAD1
B25
A25
LAD0
GND15
B26
A26
GND11
PCICLK
B27
A27
PCIRST#
LPCPD#
B28
A28
GND13
GND16
B29
A29
OSC
PME#
B30
A30
VCC3_3
VCC3_4
60Pin_CardCon
Layout Note:
Line up LPC slot
with PCI Slot 3
R225
BUF_PCI_RST# 9,15,19,20,21,29,30,31
0
J33
1
2
SMC_RUNTIME_SCI# 16,29,33
3
4
SMC_WAKE_SCI# 16,29,33
5
6
FAN_ON 29,35
7
8
SMB_THRM_CLK 5,29
9
10
SMB_THRM_DATA 5,29
11
12
13
14
SMB_SB_CLK 29,33,41
15
16
SMB_SB_DATA 29,33,41
17
18
SMB_SB_ALRT# 29,33,41
19
20
PM_BATLOW# 16,29,33
21
22
23
24
25
26
27
28
SMB_SC_INT# 29
29
30
15x2_HDR
SMC Sidebands for LPC Power Management
+V5_LPCSLOT
+V3.3 7,9,15,17,20,24,27,29,32,36,40,41
R233
C270
C261
22UF
0.1UF
B
C
16,17,18,19,21
+V3.3S_ICH
16,18,32
1
16
ICH_GPIO7
2
3
16
ICH_GPIO42
4
16
ICH_GPIO43
+V5_LPCSLOT
SMBus Debug Header
INT_SERIRQ 15,19,20,21,29,31
PM_CLKRUN# 16,18,29,31
LPC_DRQ#0 16,31
14,16,36,38
LPC_AD3 16,28,29,30,31
LPC_AD1 16,28,29,30,31
CLK_LPCPCI 14
PM_SUS_STAT# 9,16,29,31
PCI_PME# 9,15,19,20
NOTE:
Route Processor Test
signals stubless to
headers
+V3.3_LPCSLOT
0.01_1%
C287
C218
C220
C276
22UF
0.1UF
0.1UF
0.1UF
C
D
J69
1
2
3
4
3,15
H_PWRGD
5
6
15,18
SM_INTRUDER#
7
8
PM_RI#
9
10
11
12
15,18
SMB_ALERT#
13
14
3,15
H_NMI
15
16
3,15
H_SMI#
2X8_HDR
J97
CON4_HDR
17,18
+V3.3ALWAYS_ICH
16,36,38
R331
4.7K
J98
1
2
15
TP_HUB_PD11
3
4
5
6
15,18,20
INT_PIRQH#
7
8
16
ICH_MFG_MODE
9
10
9,15,19,20
PCI_PME#
2X5-Header
ICH4-M Testpoint Header
J85
1
2
PM_STPCPU#
3
4
5
6
9,16
PM_C3_STAT#
7
8
9
10
16,36
VR_PWRGD_ICH
11
12
13
14
15
16
2X8_HDR
J68
1
2
41
IDE_PPWR_EN
3
4
24,31
IDE_SPWR_EN#
5
6
7
8
8Pin HDR
SIO Sidebands
TEST HEADER
J84
1
2
16,29,31,33
SMC_EXTSMI#
3
4
36
IMVP_PWRGD
5
6
16
PM_GMUXSEL
7
8
8Pin HDR
NO STUFF
GROUND HEADERS
J96
J40
1
2
1
2
1
J95
1
2
1
Title
LPC Slot & Debug Headers
Size
Project:
A
855PM Platform
Date:
Monday, February 24, 2003
D
E
H_INIT# 3,15
H_INTR 3,15
PCI_RST# 6,15,23,28,42
H_STPCLK# 3,15
H_CPUSLP# 3,15
J70
1
14,16
PM_STPPCI#
2
16,41
PM_SLP_S5#
3
4
3,6,15
H_DPSLP#
5
PM_DPRSLPVR
6
6Pin_HDR
ICH_GPIO28 16
IDE_PATADET 16,23
IDE_SATADET 16,23
INT_IRQ14 15,18,23
INT_IRQ15 15,18,23
PM_CLKRUN# 16,18,29,31
PM_SLP_S4# 16,29,41
FWH_WP# 16,28
FWH_TBL# 16,28
PM_CPUPERF# 16
PM_SUS_CLK 16
AGP_SUSPEND# 16
J49
J82
J15
2
1
2
1
2
J11
J34
J39
2
1
2
1
2
Document Number
Rev
Sheet
34
of
47
E
4
3
2
1
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