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Platform Design Checklist
14.4.2.3.
Required Strapping when ITP Debug Port Disable
Pin Name
System
Pull up/Pull down
TCK
Pull down to GND
TDI
Pull up to VCCP
TDO
TMS
Pull up to VCCP
TRST#
Pull down to GND
NOTES:
See Section 14.4.2.1 if ITP700FLEX connector is implemented.
1.
See Section 14.4.2.3 if NO processor ITP debug port solution is implemented.
2.
Default tolerance for resistors is +/-5% unless otherwise specified.
3.
14.4.3.
Thermal Sensor
Platform recommendations and design guidelines provided by your diode thermal sensor vendor should
be adhered to ensure proper operation of your thermal sensor.
14.4.4.
Decoupling Recommendations
Signal
VCCA[3:0]
VCC[Vcc_core]
VCCP
288
ITP Interposer
27
150
39
680
Decoupling Recommendations
Configuration
F
10 µF
10 nF
220 µF
10 µF
150 µF
0.1 µF
Series Termination
Resistor (
Pull down needs to be placed within
2.0" of CPU socket.
Pull up needs to be placed within 2.0" of
CPU socket.
Leave the signal as NC (No Connect).
Pull up needs to be placed within 2.0" of
CPU socket.
Pull down needs to be placed within
2.0" of CPU socket.
1
Qty
4
VCCA[3:0] should be tied to Vcc1_8.
4
One 1206 form factor 10 µF and one 0603
form factor 10 nF capacitor pair should be
used for each VCCA pin.
See Section 5.3.1 for details on guidelines
for placement and routing of the VCCA
decoupling capacitors
4
Polymer Covered Aluminium (SP, AO
Cap)
0805 MLCC, >=X6R
35
See Section 5.9.3 for details on guidelines
for placement and routing of the
VCC[Vcc_core] decoupling capacitors.
1
Polymer Covered Tantalum (POSCAP,
Neocap, KO Cap)
10
0603 MLCC, >= X7R.
Place all capacitors next to CPU.
Also see Section 14.6.4 for VCCP
decoupling requirement at the MCH.
See Section 5.9.4 for details on Intel
processor and MCH VCCP voltage plane
®
Intel
855PM Chipset Platform Design Guide
1, 2
Notes
Notes
R
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