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Uni-Processor System Bus Routing Guidelines; System Bus Signal Groups - Intel Xeon Design Manual

Processor and e7500/e7501 chipset compatible platform. addendum for embedded applications
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Intel
2.0

Uni-processor System Bus Routing Guidelines

This section covers the system bus source synchronous (data, address, and associated strobes) and
common clock signal routing for Intel
FSB)/Low Voltage Intel
based systems, in a uni-processor (UP) configuration.
corresponding signal types.
Figure 1
describes the uni-processor system bus topology.
Table 2. System Bus Signal Groups
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
AGTL+ Source Synchronous I/O:
4X Group
AGTL+ Source Synchronous I/O:
2X Group
AGTL+ Strobes
Async GTL+ Input
Async GTL+ Output
System Bus Clock
TAP Input
TAP Output
SMBus Interface
Power/Other
NOTES:
1. These signals do not have on-die termination on the processor. They must be terminated properly on the
system board. If the signal is not connected, it must be pulled to the appropriate voltage level through a 1
kΩ ± 5% resistor.
2. Xeon processors use only BR0# and BR1#.
3. These signals are 'wired-OR' signals and may be driven simultaneously by multiple agents. For further
details on how to implement wired-OR signals, refer to the routing guidelines in
4. The value of these pins driving the active edge of RESET# determine processor configuration options.
5. SM_V
6. Terminations and routing for TAP signals and all debug port signals are found in the ITP700 Debug Port
Design Guide.
7. PROCHOT# is input/output on Low Voltage Intel® Xeon™ processor D-stepping and beyond.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
®
Xeon™ processor (400 MHz FSB) and Intel
Signal Group
Synchronous to BCLK
Synchronous to BCLK
Synchronous to
associated strobe
Synchronous to
associated strobe
Synchronous to BCLK
[1:0]
1
Asynchronous
1
Asynchronous
Clock
6
Synchronous to TCK
6
Synchronous to TCK
1
Synchronous to SM_CLK
Power/Other
has critical power sequencing requirements.
CC
®
E7500/E7501 Chipset Compatible Platform
®
Xeon™ processor with 512 KB L2 cache (400/533 MHz
Table 2
lists the signals and their
Type
BPRI#, BR[3:1]#
RS[2:0]#, RSP#, TRDY#
ADS#, AP[1:0]#, BINIT#
BPM[5:0]#
DRDY#, HIT#
MCERR#
D[63:0]#, DBI[3:0]#
A[35:3]#
ADSTB[1:0]#, DSTBN[3:0]#, DSTBP[3:0]#
A20M#, IGNNE#, INIT#
LINT1/ NMI, PWRGOOD, SMI#
STPCLK#
FERR#, IERR#, THERMTRIP#,
PROCHOT#
BCLK0, BCLK1
TCK, TDI, TMS, TRST#
TDO
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
GTLREF[3:0], COMP[1:0], OTDEN,
RESERVED, SKTOCC#, TESTHI[6:0],
VID[4:0], VCC_CPU, SM_V
V
SSA
V
SSSENSE
®
E7500/E7501 chipset-
Signals
1,2
, DEFER#, RESET#
3
3
, BNR#
,
1
1
, BR0#
, DBSY#, DP[3:0]#,
3
3
, HITM#
, LOCK#,
3
4
, REQ[4:0]#
4
, LINT0/INTR,
4
, SLP#,
7
5
, V
CC
, V
, V
, V
,
CCIOPLL
SS
CCSENSE
Section
2.2.1.
1
,
,
CCA
9

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This manual is also suitable for:

E7500E7501