Figure 76. Control Signal Routing Topology; Table 27. Control Signal Routing Guidelines - Intel 855PM Design Manual

R

Figure 76. Control Signal Routing Topology

Intel 855PM MCH
MCH
Die
The control signals should be routed using 1:2 trace to space ratio for signals within the control group.
There should be a minimum of 20-mils of spacing to non-DDR related signals and DDR clocks
SCK/SCK#[5:0]. Control signals should be routed on inner layers with minimized external trace lengths.

Table 27. Control Signal Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Trace Width
Trace to Space ratio
Group Spacing
Trace Length L1 – MCH Control Signal Ball to
SO-DIMM Pad
Trace Length L2 – SO-DIMM Pad to Parallel
Termination Resistor Pad
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via
Count Per Signal
Length Matching Requirements
NOTES:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
1.
Power distribution vias from Rt to Vtt are not included in this count.
2.
It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel termination
3.
resistor.
The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
4.
requirements.
L1 trace length does not include MCH package length and should not be used when calculating L1 length.
5.
®
Intel 855PM Chipset Platform Design Guide
MCH Pkg Route
P
SO-DIMM0,1 PAD
Parameter
System Memory Design Guidelines (DDR-SDRAM)
L1
Routing Guidelines
Control – SCKE[3:0], SCS#[3:0]
Point-to-Point with Parallel Termination
Ground Referenced
55 ±15%
Inner layers: 4 mils
Outer layers: 5 mils
1:2 (e.g. 4 mil trace to 8 mil space)
Isolation spacing for non-DDR related
signals = 20 mils minimum
Min = 0.5 inches
Max = 5.0 inches
Max = 2.0 inches
56 ± 5%
3
Control Signals to SCK/SCK#[5:0]
See Section 6.1.2.1 for details
Rt
L2
Figure
Figure 76
Figure 76
Vtt
Notes
1
4, 5
2, 3, 4
135