Intel 855PM Design Manual page 278

Platform Design Checklist
Pin Name System
Pull up/Pull
down
GTLREF
(pin AD26)
IERR# Pull up to VCCP
INIT# See Notes
PRDY#, PREQ#
PROCHOT# Pull up to VCCP
278
Intel Pentium M/Intel Celeron M Processor – Resistor Recommendations
1 k ± 1%
(top)
2 k ± 1%
(bottom)
56
56
Series Termination
Resistor (
be placed between the receiver and
termination resistor. Series resistor
should have no stub when connecting
to the FERR# trace from the CPU.
See Section 4.1.4.1.2 for more details.
Voltage divider placed within 0.5" of
CPU pin via a Zo = 55
decoupling should be placed on the pin.
See Figure 148 and section 4.1.7 for
more details.
56 IERR# is a 1.05 V tolerant signal and
voltage translation logic may be
required.
If IERR# Is NOT Used:
56 pull-up to VCCP is required.
If IERR# Is Used:
Parallel termination resistor should be
placed near the system receiver. Series
resistor should be placed between the
receiver and termination resistor. Series
resistor should have no stub when
connecting to IERR# trace from the
CPU.
See Section 4.1.4.1.1 for more details.
R1 = 1.3 k INIT# is T-split from the ICH4-M to the
CPU and FWH. A voltage translation
R2 = 330
circuit is required for the use with the
Rs = 330
Intel 82802AB/AC FWH (see Figure
149).
The voltage translation circuit shown
assumes the receiver uses a 3.3 V I/O
supply voltage.
For all other firmware devices, proper
voltage translation should be ensured.
See section 4.1.4.1.7 for more details.
If ITP700FLEX Is Used:
See Section 14.4.2.1.
If ITP Interposer Is Used:
Leave the signals as NC (No Connect).
If ITP Not Supported:
Leave the signals as NC (No Connect).
PROCHOT# is a 1.05 V tolerant signal
and voltage translation logic may be
required.
The ICH4-M's THRM# signal should not
be driven by PROCHOT#.
If Voltage Translation Is Not
Required:
®
Intel 855PM Chipset Platform Design Guide
R
1
Notes
trace. No