Undershoot/Overshoot Requirements; Debug Port Routing Guidelines; Target System Implementation - Intel Pentium III Design Manual

3.9

Undershoot/Overshoot Requirements

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage
or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge
rates. The processor can be damaged by repeated overshoot events on buffers if the charge is large
enough (i.e., if the overshoot is great enough). Determining the impact of an overshoot/undershoot
condition requires knowledge of the magnitude, the pulse direction and the activity factor (AF).
Permanent damage to the processor is the likely result of excessive overshoot/undershoot. Violating the
overshoot/undershoot guideline will also make satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be
properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O buffer models do not clamp
undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being
used to characterize the processor performance, care must be taken to ensure that ESD models do not
clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization.
Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield
excessive overshoot/undershoot.
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Refer to the latest Intel
undershoot/overshoot requirements.
3.10

Debug Port Routing Guidelines

This section describes the processor debug port, in-target probe (ITP) platform design guidelines. The
data in this chapter must be used with the information found in the "Debug Tool Specifications" chapter of
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the Intel Pentium III Processor with 512KB L2 Cache Datasheet to complete the design and layout of
the debug port.
3.10.1

Target System Implementation

The implementation guidelines given in this section will ensure a fully functional ITP debug system. The
signals involved in the ITP debug system are high speed signals and must be routed with high speed
design considerations in mind. The implementation offers flexibility in areas such as JTAG routing (i.e.,
scan chain), addition of non-ITP compliant parts, and clock rate. However, the implementation is not
flexible in system and execution signal connections.
Intel will use an ITP for internal debug and system validation and recommends that all system designs
include a debug port.
3.10.1.1 Signal Layout Guidelines
The Debug Port (TAP) is a part of the processor scan chain. It will need to be connected to the bus clock
and system bus signals. This implies that the designer will place the Debug Port within 12 inches of the
nearest processor.
There are three signal groups within the debug port as mentioned in the Intel
with 512KB L2 Cache Datasheet. Each group has a different set of layout requirements. The system
signals are special ITP-specific signals and are both inputs and outputs. The JTAG signals are system
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Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
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Pentium III Processor with 512KB L2 Cache Datasheet for detailed
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Pentium III Processor
3-9