Intel 855PM Design Manual page 9

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11.3.1.
11.4. Intel 855PM MCH / 82801DBM ICH4-M Platform Power-Up Sequence.....................248
11.4.1.
11.4.2.
11.4.3.
11.5. DDR Power Delivery Design Guidelines .....................................................................254
11.5.1.
11.5.2.
11.5.3.
11.5.4.
11.5.5.
11.5.6.
11.6. Clock Driver Power Delivery Guidelines......................................................................263
11.7. Decoupling Recommendations....................................................................................265
11.7.1.
11.7.2.
11.7.3.
11.7.4.
11.7.5.
11.7.6.
11.7.7.
11.7.8.
11.7.9.
11.8. Intel 855PM MCH Power Consumption Numbers .......................................................268
11.9. Intel 82801DBM ICH4-M Power Consumption Numbers ............................................269
11.10. Thermal Design Power ................................................................................................270
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12. Intel PRO/Wireless 2100 and Bluetooth Design Requirements .............................................271
12.1. PCB Interface Requirements .......................................................................................271
12.2. DC Power Requirements for Bluetooth .......................................................................271
12.3. Selective Suspend Support .........................................................................................272
12.4. Wake on Bluetooth Requirements ...............................................................................272
12.5. RF Disable Support Requirements for Intel PRO/Wireless 2100
and Bluetooth Devices.................................................................................................272
13. Reserved, NC, and Test Signals ..............................................................................................273
13.1. Intel Pentium M Processor and Intel Celeron M RSVD Signals ..................................273
13.2. Intel 855PM MCH RSVD Signals.................................................................................274
14. Platform Design Checklist ........................................................................................................275
14.1. General Information .....................................................................................................275
14.2. Customer Implementation............................................................................................276
14.3. Design Checklist Implementation ................................................................................276
14.4. Intel Pentium M Processor and Intel Celeron M Processor..........................................277
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Intel 855PM Chipset Platform Design Guide
Power Management States..........................................................................248
Intel 82801DBM ICH4-M Power Sequencing Requirements.......................251
11.4.1.1. 3.3/1.5 V and 3.3/1.8 V Power Sequencing..................................251
11.4.1.2. V / 3.3 V Sequencing................................................................251
5REF
11.4.1.3. V Design Guidelines .........................................................251
5REF_SUS
Intel 855PM MCH Power Sequencing Requirements..................................253
DDR Power Sequencing Requirements ......................................................253
DDR Interface Decoupling Guidelines .........................................................255
11.5.1.1. Intel 855PM MCH VCCSM Decoupling Guidelines ......................255
11.5.1.2. DDR SO-DIMM System Memory Decoupling Guidelines.............255
2.5-V Power Delivery Guidelines .................................................................255
DDR Reference Voltage...............................................................................256
11.5.3.1. SMVREF Design Recommendations............................................259
11.5.3.2. DDR VREF Requirements ............................................................261
DDR SMRCOMP Resistive Compensation .................................................262
DDR VTT Termination..................................................................................262
DDR SMRCOMP, SMVREF, VTT 1.25-V Supply Disable in S3/Suspend ..262
11.5.6.1. VTT Rail Power Down Sequencing During Suspend ...................262
11.5.6.2. VTT Rail Power Up Sequencing During Resume .........................263
Processor Decoupling Guidelines................................................................265
Intel 855PM MCH Decoupling Guidelines....................................................265
Intel 82801DBM ICH4-M Decoupling Guidelines.........................................265
DDR VTT High Frequency and Bulk Decoupling.........................................267
AGP Decoupling...........................................................................................267
Hub Interface Decoupling.............................................................................267
FWH Decoupling ..........................................................................................267
General LAN Decoupling .............................................................................267
CK-408 Clock Driver Decoupling .................................................................268
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