Processor Pll Voltage Supply Power Sequencing; Voltage Identification For Intel Pentium M/Intel Celeron M Processor; Figure 46. Processor 1.8 V Vcca[3:0] Recommended Power Delivery And Decoupling - Intel 855PM Design Manual

Platform Power Requirements

Figure 46. Processor 1.8 V VCCA[3:0] Recommended Power Delivery and Decoupling

LAYER 3 LAYER 3 LAYER 3 LAYER 3
1.8V from 1.8V from
1.8v from 1.8v from 1.8v from 1.8v from 1.8v from 1.8v from
Intel 855PM Intel 855PM
855PM 855PM 855PM 855PM 855PM 855PM
MCH MCH
5.3.2.

Processor PLL Voltage Supply Power Sequencing

See Section 11.4.2 for more details on platform power sequencing requirements for the 1.8-V supply to
the processor and Intel 855PM MCH's PLLs.
5.3.2.1.

Voltage Identification for Intel Pentium M/Intel Celeron M Processor

There are six voltage identification pins on the Intel Pentium M/Intel Celeron M processor. These
signals can be used to support automatic selection of V
support voltage specification variations on current and future processors. VID[5:0] is defined in Table
19 below.
The VID[5:0] signals are 1.05-V CMOS level outputs. Intel recommends that 1:2 spacing and routing
with a trace impedance of 55
guarantee signal quality, a point-to-point routing between the Intel processor and the VRM should be
used. Figure 47 illustrates a signal escape routing example in the vicinity of the processor package
outline. To allow for the coexistence of V
routing, the VID[5:0] signals should utilize the remainder of the routing channels on Layer 3 ( for VID2
and VID0), Layer 6 (for VID4), and Layer 8 (for VID1, VID3, and VID5).
94
GTLREF0 GTLREF0 GTLREF0 GTLREF0 GTLREF0 GTLREF0
VCCA3 VCCA3 VCCA3 VCCA3 VCCA3 VCCA3
VCCA0 VCCA0 VCCA0 VCCA0 VCCA0 VCCA0
CC-CORE
± 15% be used. No external termination is required for VID[5:0]. To
and V power delivery routing as well as FSB signal
CC-CORE CCP
Intel
PRIMARY SIDE PRIMARY SIDE PRIMARY SIDE PRIMARY SIDE
VCCA2 VCCA2 VCCA2 VCCA2 VCCA2 VCCA2
VCCA1 VCCA1 VCCA1 VCCA1 VCCA1 VCCA1
voltages. They are needed to cleanly
®
855PM Chipset Platform Design Guide
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