Topology 1A: Open Drain (Od) Signal Driven By The Processor - Ierr; Figure 16. Routing Illustration For Topology 1A; Table 8. Layout Recommendations For Topology 1A - Intel 855PM Design Manual

FSB Design Guidelines
4.1.4.1.1. Topology 1A: Open Drain (OD) Signal Driven by the Processor – IERR#
The Topology 1A OD signal IERR# should adhere to the following routing and layout
recommendations. Table 8 lists the recommended routing requirements for the IERR# signal of the
processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using
55 ± 15% characteristic trace impedance. Series resistor R1 is a dampening resistor for reducing
overshoot/undershoot reflections on the transmission line. The pull-up voltage for termination resistor
Rtt is V
CCP
implemented in a number of ways to meet design goals. IERR# can be routed as a test point or to any
optional system receiver.

Figure 16. Routing Illustration for Topology 1A

Table 8. Layout Recommendations for Topology 1A

L1
0.5" – 12.0"
0.5" – 12.0"
52
(1.05 V). Due to the dependencies on system design implementation, IERR# can be
Intel
Pentium M
processor
L2 L3
0" – 3.0" 0" – 3.0"
0" – 3.0" 0" – 3.0"
System
Receiver
L2
R1
L1
R1
56 ± 5%
56 ± 5%
®
Intel 855PM Chipset Platform Design Guide
VCCP
Rtt
L3
Transmission Line
Rtt
Type
56 ± 5% Micro-strip
56 ± 5% Strip-line
R