Intel 855PM Design Manual page 291

R
Pin Name
Pull up/Pull down
REF
SEL[2:1] Pull down to GND
SEL[0] Pull up to Vcc3_3
USB
XTAL_IN
See Notes
XTAL_OUT
See Notes
VDD[7:0], VDDA Tie to Vcc3_3
See Notes
VSS[5:0] Tie to GND
VSSA Tie to GND
VSSIREF Tie to GND
NOTE: Default tolerance for resistors is +/-5% unless otherwise specified.
®
Intel 855PM Chipset Platform Design Guide
CK-408 Clock – Resistor Recommendations
System
1K
1K
None
None
CK-408 Clock – Power Signals
CK-408 Clock – GND Signals
Series Resistor
(
This signal should be driven by the ICH4-
M's SLP_S3# signal.
33 If the signal is used, one 33
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
See Section 10.2.7 for routing
requirements.
33 If the signal is used, one 33
resistor is required for each receiver.
If NOT used, this signal can be left as NC
(No Connect).
Connect to XTAL_OUT through a 14.318
MHz clock. Place crystal within 500 mils of
CK-408.
Connect to XTAL_IN through a 14.318
MHz clock. Place crystal within 500 mils of
CK-408.
Also see Section 14.5.2 for decoupling
requirement.
Platform Design Checklist
Notes
series
series
291