Itp Interposer Design Guidelines For Production Systems; Logic Analyzer Interface (Lai); Figure 44. Itp_Clk To Cpu Itp Interposer Layout Example - Intel 855PM Design Manual

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Figure 44. ITP_CLK to CPU ITP Interposer Layout Example

33Ω 33Ω
PRIMARY SIDE PRIMARY SIDE
4.3.2.2.

ITP Interposer Design Guidelines for Production Systems

For production systems that do not use the ITP interposer, the following guidelines should be followed
to ensure that all necessary signals are terminated properly.
Table 16 summarizes all the signals that require termination when a system does not utilize the ITP
interposer. This includes TDI, TMS, TRST#, and TCK. TDO can be left as a no connect.
The series 33
host clock inputs to the processor socket can also be depopulated for production systems. The only
requirement is that the BIOS should disable the third differential host clock pair routed from the CK-408
clock chip to the Intel Pentium M processor / Intel Celeron M processor socket.
Finally, the 150- to 240- pull-up resistor for the DBR# output signal from processor socket may or
may not be depopulated depending on how it affects the system reset logic that it is connected to. Thus,
it is the responsibility of the system designer to determine whether termination for DBR# is required or
not for a given system implementation. The same is also true for DBA#, if implemented. It is the
responsibility of the system designer to determine whether termination for DBA# is required or not.
4.3.3.

Logic Analyzer Interface (LAI)

Intel is working with Agilent* Corporation to provide logic analyzer interfaces (LAIs) for use in
debugging Intel Pentium M/Intel Celeron M processor-based systems. LAI vendors should be contacted
to get specific information about their logic analyzer interfaces. The following information is general in
nature. Specific information must be obtained from the logic analyzer vendor.
Due to the complexity of an Intel Pentium M/Intel Celeron M processor-based system, the LAI is critical
in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in
mind when designing an Intel Pentium M/Intel Celeron M processor-based system that can make use of
an LAI: mechanical and electrical.
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Intel 855PM Chipset Platform Design Guide
A16, A15 pins A16, A15 pins
49.9Ω 49.9Ω
CK-408 CK-408
LAYER 6 LAYER 6
and 49.9 ±1% parallel termination resistors on the ITP_CLK/ITP_CLK# differential
FSB Design Guidelines
ITP_CLK ITP_CLK
ITP_CLK# ITP_CLK#
SECONDARY SECONDARY
SIDE SIDE
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