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5.
Platform Power Requirements
5.1.
General Description
The Intel Pentium M processor supports Enhanced Intel
time dynamic switching of the voltage and frequency between multiple performance modes. This occurs
by switching the bus ratios, core operating voltage, and core processor speeds without resetting the
system. With Enhanced Intel
The processor will be able to operate in more than two voltage levels. Although this specification
addresses the highest processor core frequency and the lowest processor core frequency, there will be
other modes where the voltage command may be different than that of these two modes. The Intel
Celeron M processor does not support Enhanced Intel SpeedStep technology.
Terminology used to reference the names of the voltage rails are defined below.
V
CC-CORE
V
is the FSB rail of the processor and MCH. Also used for CPU signals of ICH4-M chipset and
CCP
CPU ITP700FLEX debug port if used
V
CC-MCH
5.2.
Intel 855PM MCH Phase Lock Loop Power Delivery
Design Guidelines
5.2.1.
Intel 855PM MCH PLL Power Delivery
V
and V
CCGA
on the MCH silicon. Since these PLLs are analog in nature, they require quiet power supplies for
minimum jitter. Jitter is detrimental to the system; it degrades external I/O timings as well as internal
core timings (i.e. maximum frequency). Traditionally these supply pins are low-pass filtered to prevent
any performance degradation. The MCH has an internal super filter for the 1.8-V analog supply. Thus,
the MCH does not require any external low-pass filtering for these power pins. However, one 10-nF
0603 form factor and one 10- F 1206 form factor decoupling capacitor should be placed as close as
possible to the VCCGA and VCCHA pins. It is acceptable to share one of the capacitors from each of
the listed types above for the two pins as long as a robust connection between the two pins is made. An
example of such a connection is shown below. The VCCGA and VCCHA pins will share the 1.8-V
power plane of the Hub Interface. However, it is advisable to connect the VCCGA and VCCHA pins
with a separate flood that will "fork out" from the bulk decoupling capacitors of the HI 1.8 V power
supplies and will route as a separate flood plane to the VCCGA and VCCHA pins without sharing the
power delivery pins of the MCH Hub Interface's 1.8 V. To minimize inductance and resistance
parasitics, a flood with maximal width should be used along with 25-mil wide dog bone connections to
vias that connect BGA lands on the primary side.
In Figure 45, the recommended power delivery layout and decoupling for VCCGA and VCCHA is
shown. Notice on the left side of Figure 45 how the 1.8-V supply that powers the Hub Interface forks
®
Intel
855PM Chipset Platform Design Guide
SpeedStep
®
is the core rail of the processor
is the core rail of the MCH
are two pins on the Intel 855PM MCH that supply power to the PLL clock generators
CCHA
SpeedStep
®
technology, there will be more than two modes of operation.
®
Platform Power Requirements
technology, which enables real-
®
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