Table 5. Bclk [1:0] Routing Guidelines - Intel Pentium 4 Design Manual

R
EMI constraints
Clocks are a significant contributor to EMI and should be treated with care. Following these
recommendations can aid in EMI reduction:
• Route clocks on inner layers.
• On internal signals layers maintain a minimum of 100 mils from the edge of the clock traces to
the edge of the system board.
• Maintain uniform spacing between the two halves of differential clocks
• Route clocks on a physical layer adjacent to the VSS reference plane only
• Spread spectrum clocking (SSC) should be enabled to reduce the magnitude of EMI.
Table 5 describes the routing guidelines for the bus clock signals.

Table 5. BCLK [1:0] Routing Guidelines

Layout Guideline
BCLK Skew between agents
Differential pair spacing
Spacing to other traces
Line width
System board Impedance –
Differential
System board Impedance – single
ended
Processor routing length –
L1, L1': Clock driver to Rs
Processor routing length –
L2, L2': Rs to Rs-Rt node
Processor routing length –
L3: RS-RT node to Rt
Processor routing length –
L4, L4': RS-RT Node to Load
MCH routing length –
L1: Clock Driver to RS
MCH routing length –
L2, L2': Rs to Rs-Rt node
MCH routing length –
L3: RS-RT node to Rt
MCH routing length –
L4, L4': RS-RT Node to Load
® ®
Intel Pentium 4 Processor / Intel
400 ps total
Budget:
150 ps for Clock driver
250 ps for interconnect
7.0 mils
20 mils
7.0 mils
100 Ω
50 Ω ±15%
0.5 inches max
0 – 0.2 inches
0 – 0.2 inches
0 – 12 inches
0.5 inches max
0 – 0.2 inches
0 – 0.2 inches
0 – 12 inches
®
850 Chipset Family Platform Design Guide
Platform Clock Routing Guidelines
Value Illustration
Figure 12
Figure 15
Figure 15
Figure 15
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—
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
Notes
1, 2, 3, 4
5, 6
—
7
8
9
12
12
12
12
12
12
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