Trace Geometry And Length; Signal Isolation; Figure 124. Trace Routing - Intel 855PM Design Manual

I/O Subsystem

Figure 124. Trace Routing

9.9.6.1.1.

Trace Geometry and Length

The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to
trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers
that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace
width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the
width of the trace should be modified when changing from one board layer to another if the two layers
are not equidistant from the power or ground plane. Differential trace impedances should be controlled
to be ~100 . It is necessary to compensate for trace-to-trace edge coupling, which can lower the
differential impedance by up to 10 , when the traces within a pair are closer than 30 mils (edge to
edge).
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and
thin traces are more inductive and would reduce the intended effect of decoupling capacitors. Also for
similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the
decoupling capacitors should be sufficiently large in diameter to decrease series inductance.
Additionally, the PLC should not be closer than one inch to the connector/magnetics/edge of the board.
9.9.6.1.2.

Signal Isolation

Some rules to follow for signal isolation:
Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils
between all differential pairs (Ethernet) and other nets, but group associated differential pairs
together. NOTE: Over the length of the trace run, each differential pair should be at least 0.3
inches away from any parallel signal traces.
Physically group together all components associated with one clock trace to reduce trace length and
radiation.
Isolate I/O signals from high speed signals to minimize crosstalk, which can increase EMI emission
and susceptibility to EMI from other signals.
Avoid routing high-speed LAN traces near other high-frequency signals associated with a video
controller, cache controller, CPU, or other similar devices.
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Intel 855PM Chipset Platform Design Guide
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Trace Routing