Asynchronous Signals; Topologies; Figure 15. Trace Length Equalization Procedures With Allegro - Intel 855PM Design Manual

R
7. Use the Allegro* "Move ix" (i.e. if vertical routing) command to move the floating section by
the /2 distance listed in cell B4.
8. Reconnect the floating segment if needed.
9. Repeat steps 5 through 8 for the reminder of the traces in the group

Figure 15. Trace Length Equalization Procedures with Allegro*

REFERENCE LENGTH
STARTING LENGTH
∆
∆/2
4.1.4.

Asynchronous Signals

4.1.4.1.

Topologies

The following sections describe the topologies and layout recommendations for the Asynchronous Open
Drain and CMOS Signals found on the platform.
All Open Drain signals listed in the following sections below must be pulled-up to V
of these Open Drain signals are pulled-up to a voltage higher than V
consumption of the processor may be affected. Therefore, it is very important to follow the
recommended pull-up voltage for these signals.
®
Intel 855PM Chipset Platform Design Guide
CUT
5950
6012
-62
-31
∆=Starting Length – Reference Length
FSB Design Guidelines
Move ix - ∆/2
(1.05 V). If any
CCP
, the reliability and power
CCP
51