Agp Busy/Stop Design Requirements - Intel 855PM Design Manual

R
GPIO[43:32]:
I/O balls. From main power well (V
Default as outputs when enabled as GPIOs
These signals are NOT 5-V tolerant
GPIO[32] can be used as AGP_SUSPEND#
GPIO[33] can be used as KSC_VPPEN#
GPIO[34] can be used as SER_EN
GPIO[35] can be used as FWH_WP#
GPIO[36] can be used as FWH_TBL#
GPIO[40] can be used as IDE_PATADET
GPIO[41] can be used as IDE_SATADET
14.8.3.

AGP Busy/Stop Design Requirements

Signal
AGPBUSY#
C3_STAT#
SUS_STAT#
NOTE: Please also consult Intel for the latest AGP Busy and Stop signal implementation.
®
Intel 855PM Chipset Platform Design Guide
AGP Busy/Stop design requirements
System
Pull up/Pull down
Pull up to Vcc3_3 10 k
No pull up/pull down
required.
See notes
No pull up/pull down
required.
See notes
3_3).
CC
This ICH4-M signal requires a pull up to the switched
3.3-V rail (the 3.3V power rail which will be powered
OFF during S3).
This ICH4-M signal must be connected to the
AGP_BUSY# output of the external AGP Graphics
Controller.
When an external AGP device is enabled, this signal
must be connected from ICH4-M to the external AGP
Graphics Controller for STP_AGP# signal
implementation.
When an external AGP device is enabled, this signal
must be connected from ICH4-M to the external AGP
Graphics Controller if the AGP device is designed to
use this signal.
Assertion of this ICH4-M signal indicates that the
system will be entering one of the S1-S5 low-power
states, and that the platform clocks (including the AGP
clock) will soon stop toggling.
This signal can be monitored by devices with memory
that need to switch from normal refresh to suspend
refresh mode. It can also be used as an indication that
the peripherals should isolate their outputs that may be
going to powered-off planes.
Platform Design Checklist
Notes
309