Figure 72. Data Signal Routing Topology; Table 24. Data Signal Group Routing Guidelines - Intel 855PM Design Manual

R
termination resistor, or transition to same internal layer and then return to external layer and connect to
the parallel termination resistor.
The data signal group byte lane and associated strobe needs to be routed on the same inner signal layer.
The data signal groups and associated strobe may be routed on different internal layers provided that the
byte lane are all routed on same internal layer. For example SDQ[7:0] and SDQS0 may be routed on
one internal layer and SDQ[15:8] and SDQS1 may be routed on a different internal layer. In addition,
match routing topology and via placement for all signals in a given byte lane including the associated
strobe. External trace lengths should be minimized. To facilitate simpler routing, swapping of the byte
lane and the associated strobe is allowed for SDQ[63:0] only. Bit swapping within the byte lane is
allowed for SDQ[63:0] only. The CB group, SDQ[71:64], cannot be byte lane swapped with another
DQ byte late. Also, bit swapping within the SDQ[71:64] byte lane is not allowed. All internal and
external signals should be ground referenced to keep the path of the return current continuous.
Resistor packs are acceptable for the series (Rs) and parallel (Rt) data and strobe termination resistors,
but data and strobe signals can't be placed within the same R pack as the command or control signals.
The table and diagrams below depict the recommended topology and layout routing guidelines for the
DDR-SDRAM data signals.

Figure 72. Data Signal Routing Topology

Intel 855PM MCH
MCH
Die
The data signals should be routed using 1:2 trace to space ratio for signals within the data group. There
should be a minimum of 20 mils of spacing to non-DDR related signals and DDR clock pairs
SCK/SCK#[5:0]. Data signals should be routed on inner layers with minimized external trace lengths.

Table 24. Data Signal Group Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Trace Width
Trace to Space ratio
Group Spacing
Trace Length L1 – MCH Signal Ball to Series
Termination Resistor Pad
Trace Length L2 – Series Termination Resistor
®
Intel 855PM Chipset Platform Design Guide
MCH Pkg Route
P
L 1
Parameter
System Memory Design Guidelines (DDR-SDRAM)
R s
L2
L3
SO-DIMM0 PAD
Routing Guidelines
Data – SDQ[71:0], SDQS[8:0]
Daisy Chain with Parallel Termination
Ground Referenced
55 ±15%
Inner layers: 4 mils
Outer layers: 5 mils
1:2 (e.g. 4 mil trace to 8 mil space)
Isolation spacing for non-DDR related
signals = 20 mils minimum
Min = 0.5"
Max = 3.75"
Max = 0.75"
V tt
R t
L4
SO-DIMM1 PAD
Figure Notes
1
6
Figure 74 3, 5
Figure 74 3
127