Pciclk Clock Group; Figure 134. Clk33 Group Topology; Table 66. Clk33 Group Routing Guidelines - Intel 855PM Design Manual

R

Figure 134. CLK33 Group Topology

Clock
Driver

Table 66. CLK33 Group Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Trace Width
Trace to Space Ratio
Group Spacing
Trace Length – A
Trace Length – B
Series Termination Resistor (R1)
Skew Requirements
NOTES:
Recommended resistor values and trace lengths may change in a later revision of the design guide.
1.
10.2.5.

PCICLK Clock Group

The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock
input buffer at the PCI devices on the PCI cards. Note that the goal is to have a maximum of ±1 ns skew
between the clocks within this group, and also a maximum of ± 1 ns skew between the clocks of this
group and that of group CLK33.
®
Intel 855PM Chipset Platform Design Guide
A
Parameter
Platform Clock Routing Guidelines
R1
B
Routing Guidelines
CLK33
Point-to-Point
Ground Referenced (Contiguous over entire
length)
55 ± 15%
4 mils
1:5 (e.g. 4 mils trace 20 mils space)
Isolation spacing from non-Clock signals =
20 mils minimum
Must be exactly trace length matched to
CLK66 Trace A
Must be exactly trace length matched to
CLK66 Trace B
33 ± 5%
Minimal skew (~ 0) between CLK33 group
and CLK66 group
ICH4-M,
SIO,
FWH
Figure Notes
1
Figure 134
Figure 134
Figure 134
239