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R
11.5.3.2.
DDR VREF Requirements
Making the same calculations for the DDR loading, results to find the max VREF load of 1 mA, a
divider is STILL NOT feasible here as the load of 1mA causes unacceptable drop across even a small
Rs, which wastes power.
Table 80. DDR VREF Calculation
Name
Purpose
VOLTAGE Nominal (V)
TOLERANCE (+/-V)
Vmax(V)
Vmin(V)
Design Guide
NOTE:
The DDR core is called "Vdd" =+2.5 V ± 8% (= ± 0.2 V). VREF is ("Vdd" ± 8%)/2 ± 50 mV. This means that
whether the 2.5 V is 8% high or low, Platform designers need to be able to divide that voltage by 2 within an
accuracy of 50 mV. This basically means to use 1% resistors, or better.
Table 81. Reference Distortion Due to Load Current
R( )
1
10
100
1000
10000
100000
1000000
NOTE:
As for the MCH, a calculation can be made for the DDR. This shows that even with the slight load of 1 mA by
the DDR it is still not feasible to use a simple resistor divider. Using the max leakage specs provided today
and trying to maintain an error of less than 1% (12.5 mV) one needs to decrease the resistor values such
that the current just to source the divider becomes unacceptable. A divider alone does not become an
acceptable solution until current requirements are in the 100-µA range. Today, it is not possible to guarantee
this type of current requirement for these applications. Therefore, the use of a buffer is highly recommended
for these reference voltage requirements.
®
Intel
855PM Chipset Platform Design Guide
Vdd
Core Supply Voltage, Static
Vdd
2.500 (± 8%)
0.200
2.700
2.300
I
DD
5.000
I(A)
Vdroop(V)
0.001
0.001
0.001
0.01
0.001
0.1
0.001
1
0.001
10
0.001
100
0.001
1000
Platform Power Delivery Guidelines
Vref
I/O Reference Supply Voltage, Static
Vref = (Vdd +/- 8%) / 2
1.250
0.050
1.300
1.200
I
REF
0.001
I(2.5) total=2.5 V/2R(A)
1.25
0.125
0.0125
0.00125
0.000125
1.25E-05
1.25E-06
261
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