Table 1. Fsb Common Clock Signal Internal Layer Routing Guidelines - Intel 855PM Design Manual

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Table 1. FSB Common Clock Signal Internal Layer Routing Guidelines

Signal Names
CPU
ADS#
BNR#
BPRI#
BR0#
DBSY#
DEFER#
DPWR#
DRDY#
HIT#
HITM#
LOCK#
RS[2:0]#
TRDY#
RESET#
NOTE: For topologies where an ITP700FLEX debug port is implemented, see Section 4.1.5 for RESET#
(CPURST#) implementation details.
®
Intel 855PM Chipset Platform Design Guide
Transmission Line
Type
MCH
ADS# Strip-line
BNR# Strip-line
BPRI# Strip-line
BREQ0# Strip-line
DBSY# Strip-line
DEFER# Strip-line
DPWR# Strip-line
DRDY# Strip-line
HIT# Strip-line
HITM# Strip-line
HLOCK# Strip-line
RS[2:0]# Strip-line
HTRDY# Strip-line
1 CPURST# Strip-line
Total Trace Length
Nominal
Impedance
Min Max
(inches) (inches)
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
1.0 6.5 55 ± 15%
FSB Design Guidelines
Width &
spacing
( ) (mils)
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
4 & 8
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