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AGP Port Design Guidelines
In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias
that transition the AGP signal from one reference signal plane to another. One extra 0.01-±F capacitor
per 10 vias is required. The capacitor should be placed as close as possible to the center of the via field.
7.3.5.
AGP Routing Ground Reference
Intel strongly recommends that at least the following critical signals be referenced to ground from the
MCH to an AGP controller connector using a minimum number of vias on each net: AD_STB0,
AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and
ST[2:0].
In addition to the minimum signal set listed previously, Intel strongly recommends that half of all AGP
signals be referenced to ground, depending on the board layout. In an ideal design, the complete AGP
interface signal field would be referenced to ground. This recommendation is not specific to any
particular PCB stack-up, but should be applied to all systems incorporating the Intel 855PM chipset.
7.3.6.
Pull-ups
The AGP 2.0 Specification requires AGP control signals to have pull-up resistors to VDDQ to ensure
they contain stable values when no agent is actively driving the bus. Also, the AD_STB[1:0]# and
ST_STB# strobes require pull-down resistors to GND. The Intel 855PM MCH has integrated many of
these pull-up/pull-down resistors on the AGP interface and a few other signals not required by the AGP
2.0 Specification. Pull-ups are allowed on any signal except AD_STB[1:0]# and ST_STB#.
The MCH has no support for the PERR# and SERR# pins of an AGP graphics controller that supports
PERR# and SERR#. Pull-ups to a 1.5-V source are required down on the motherboard in such cases.
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Intel
855PM Chipset Platform Design Guide
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