Lom (Lan On Motherboard) Point-To-Point Interconnect; Signal Routing And Layout; Figure 118. Single Solution Interconnect; Table 59. Lan Lom Routing Summary - Intel 855PM Design Manual

I/O Subsystem
9.9.2.1.1.

LOM (LAN On Motherboard) Point-To-Point Interconnect

The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET
are uniquely installed.

Figure 118. Single Solution Interconnect

Table 59. LAN LOM Routing Summary

Trace Impedance
55 ± 15%
9.9.2.2.

Signal Routing and Layout

Platform LAN Connect Interface signals must be carefully routed on the motherboard to meet the timing
and signal quality requirements of this interface specification. The following are some general
guidelines that should be followed. Intel recommends that the board designer simulate the board routing
to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
On the motherboard the length of each data trace is either equal in length to the LAN_CLK trace or up
to 0.5 inches shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard
trace in each group.)
214
Intel
ICH4-M
LAN Routing
Requirements
5 on 10
L
LAN_CLK
LAN_RSTSYNC
LAN_RXD[2:0]
LAN_TXD[2:0]
Maximum Trace Signal
Length Referencing
4.5 to 12 inches Ground
®
Intel 855PM Chipset Platform Design Guide
R
Platform
LAN
Connect
(PLC)
LAN Signal Length Matching
Data signals must be equal to
or no more than 0.5 inches
(500 mils) shorter than the
LAN clock trace.