Common Physical Layout Issues - Intel 855PM Design Manual

I/O Subsystem
9.9.6.2.

Common Physical Layout Issues

Here is a list of common physical layer design and layout mistakes in LAN on motherboard designs.
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise
and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. (Each component and/or via
that one trace encounters, the other trace must encounter the same component or a via at the same
distance from the PLC.) Asymmetry can create common-mode noise and distort the waveforms.
3. Excessive distance between the PLC and the magnetics or between the magnetics and the RJ-45
connector. Beyond a total distance of about 4 inches, it can become extremely difficult to design
a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy substrate) will attenuate the
analog signals. In addition, any impedance mismatch in the traces will be aggravated if they are
longer (see #9 below). The magnetics should be as close to the connector as possible (≤ one inch).
4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the transmit
channel can cause excessive emissions (failing FCC) and can cause poor transmit BER on long
cables. At a minimum, other signals should be kept 0.3 inches from the differential traces.
5. Routing the transmit differential traces next to the receive differential traces. The transmit trace
that is closest to one of the receive traces will put more crosstalk onto the closest receive trace and
can greatly degrade the receiver's BER over long cables. After exiting the PLC, the transmit traces
should be kept 0.3 inches or more away from the nearest receive trace. The only possible
exceptions are in the vicinities where the traces enter or exit the magnetics, the RJ-45, and the
PLC.
6. Use of an inferior magnetics module. The magnetics modules that we use have been fully tested
for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior
magnetics modules often have less common-mode rejection and/or no auto transformer in the
transmit channel.)
7. Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations
and decoupling are different. There are also differences in the receive circuit. Please follow the
appropriate reference schematic or Application Note.
8. Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45 and for
the wire-side center-taps of the magnetics modules. These unused RJ pins and wire-side center-
taps must be correctly referenced to chassis ground via the proper value resistor and a capacitance
or termplane. If these are not terminated properly, there can be emissions (FCC) problems, IEEE
conformance issues, and long cable noise (BER) problems. The Application Notes have
schematics that illustrate the proper termination for these unused RJ pins and the magnetics
center-taps.
9. Incorrect differential trace impedances. It is important to have ~100- impedance between the
two traces within a differential pair. This becomes even more important as the differential traces
become longer. It is very common to see customer designs that have differential trace impedances
between 75
differential impedance, many impedance calculators only multiply the single-ended impedance by
two. This does not take into account edge-to-edge capacitive coupling between the two traces.
When the two traces within a differential pair are kept close
lower the effective differential impedance by 5
common.) Short traces will have fewer problems if the differential impedance is a little off.
10. Use of capacitor that is too large between the transmit traces and/or too much capacitance from
the magnetic's transmit center-tap (on the Intel 82562ET side of the magnetics) to ground. Using
capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time
so much that they fail the IEEE rise time and fall time specs. This will also cause return loss to fail
224
and 85 , even when the designers think they've designed for 100 . (To calculate
†
to each other, the edge coupling can
- 20 . A 10- - 15- drop in impedance is
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