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Summary of Contents for Intel 852GM
- Page 1 ® Intel 852GM Chipset Platform Design Guide ® ® ® For Use with the Mobile Intel Pentium 4 Processor-M, Mobile Intel ® Celeron Processor on .13 Micron Process in the 478-Pin Package, and ® ® Intel Celeron M Processor January 2005...
- Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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Page 3: Table Of Contents
General Design Considerations ....................27 3.1. Nominal Board Stack-Up ....................27 3.2. Alternate Stack Ups .......................29 Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines...........................31 4.1. Processor Front Side Bus (FSB) Routing Guidelines............31 4.1.1. Return Path Evaluation ..................33 4.2. - Page 4 4.5. Mobile Intel Pentium 4 Processor–M and Intel 852GM Chipset FSB Signal Package Lengths ......................... 46 4.5.1. Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing Recommendations..................50 4.5.2. AGTL+ I/O Buffer Compensation ..............50 4.5.2.1. Mobile Intel Pentium 4 Processor–M AGTL+ I/O Buffer Compensation ................
- Page 5 8.1.4. RAMDAC Routing Guidelines ..............131 8.1.5. DAC Power Requirements ................133 8.1.6. HSYNC and VSYNC Design Considerations..........134 8.1.7. DDC and I2C Design Considerations ............134 8.2. LVDS Transmitter Interface ..................134 8.2.1. Length Matching Constraints ...............135 ® Intel 852GM Chipset Platform Design Guide...
- Page 6 USB 2.0 Guidelines and Recommendations............... 164 10.4.1. Layout Guidelines ..................164 10.4.1.1. General Routing and Placement ..........164 10.4.1.2. USB 2.0 Trace Separation............165 10.4.1.3. USBRBIAS Connection ..............165 10.4.1.4. USB 2.0 Termination ..............166 ® Intel 852GM Chipset Platform Design Guide...
- Page 7 10.9.1.4. Impedances...................183 10.9.1.5. Line Termination ................184 10.9.1.6. Terminating Unused LAN Connect Interface Signals ....184 10.9.2. Intel 82562ET / Intel 82562 EM Guidelines ..........184 10.9.2.1. Guidelines for Intel 82562ET / Intel 82562EM Component Placement ..................184 10.9.2.2. Crystals and Oscillators ..............184 10.9.2.3.
- Page 8 11.2.7. SSCCLK Clock Group ................. 207 11.2.8. USBCLK Clock Group ................. 208 11.3. CK-408 Clock Updates for Intel Celeron M Processor Platforms ....... 209 11.4. CK-408 PWRDWN# Signal Connections ..............209 Intel 852GM Platform Power Delivery Guidelines..............211 12.1. Definitions........................211 12.2.
- Page 9 General Information .....................237 14.2. Customer Implementation of Voltage Rails ..............237 14.3. Design Checklist Implementation ................238 14.4. Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor ....239 14.4.1. Resistor Recommendations.................239 14.4.2. In Target Probe (ITP) ...................242 14.4.3. Decoupling Recommendations ..............242 14.4.4.
- Page 10 Downstream Power Connection ..............267 14.10. FWH Checklist......................268 14.10.1. Resistor Recommendations ................ 268 14.11. LAN / HomePNA Checklist..................269 14.11.1. Resistor Recommendations (for 82562ET / 82562EM) ......269 14.11.2. Decoupling Recommendations..............269 Schematics..........................271 ® Intel 852GM Chipset Platform Design Guide...
- Page 11 Figure 17. Voltage Translation Circuit for 3.3-V Receivers ............. 45 Figure 18. GTLREF Routing....................50 Figure 19. Mobile Intel Pentium 4 Processor-M COMP[1:0] Resistive Compensation ... 51 Figure 20. Common Clock Topology..................55 Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5 ..... 57 Figure 22.
- Page 12 Figure 95. ICH4-M/Platform LAN Connect Section ............... 181 Figure 96. Single Solution Interconnect ................. 182 Figure 97. LAN_CLK Routing Example ................. 183 Figure 98. Intel 82562ET / Intel 82562EM Termination ............185 Figure 99. Critical Dimensions for Component Placement............ 185 ®...
- Page 13 Figure 137. Mobile Intel Pentium 4 Processor-M Power Up Sequence........ 244 Figure 138. Routing Illustration for INIT# (for Intel Celeron M Processor)......246 Figure 139. Voltage Translation Circuit for PROCHOT# (for Intel Celeron M Processor) ..246 Figure 140. Clock Power-down Implementation ..............248 Figure 141.
- Page 14 Table 10. Layout Recommendations for Topology 2C ............44 Table 11. Layout Recommendations for Topology 3 ............... 45 Table 12. Mobile Intel Pentium 4 Processor-M and Intel 852GM Chipset Package Lengths.. 46 Table 13. FSB Common Clock Signal Internal Layer Routing Guidelines ......54 Table 14.
- Page 15 Table 95. ICH4-M Decoupling Requirements ............... 231 Table 96. Processor “Intel Reserved” Signal Pin-Map Locations ......... 233 Table 97. Intel 852GM RSVD and NC Signal Pin-Map Locations ........234 Table 98. Mobile Intel Pentium 4 Processor-M Power-up Timing Specifications ....243 ®...
- Page 16 Table 99. GST[1:0] Configurations ..................255 Table 100. Intel 852GM GMCH Power-up Timing Specifications.......... 256 Equations Equation 1. Calculation to Determine Package Delta Addition to Motherboard Length for UP Systems ........................34 ® Intel 852GM Chipset Platform Design Guide...
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Page 17: Revision History
Revisions include: 252338 January 2004 • Added support for the Intel Celeron M Processor Revisions include: 252338 January 2005 • Updated sheets 40 and 41 of the Intel Celeron M / 852GM CRB schematics ® Intel 852GM Chipset Platform Design Guide... - Page 18 This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 19: Introduction
Introduction Introduction ® This design guide organizes and provides Intel’s design recommendations for the Intel 852GM chipset based systems. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. -
Page 20: Referenced Documents
Total Cost of Ownership Time Domain Reflectometry UBGA Micro Ball Grid Array Universal Serial Bus Voltage Regulator Module 1.2. Referenced Documents Contact your Intel Field Representative for the latest revsions. Document Location ® ® http://developer.intel.com Mobile Intel Pentium 4 Processor –M Datasheet (250686) ®... -
Page 21: System Overview
2.1. Intel 852GM Chipset Platform System Features The Intel 852GM chipset contains two core components: the Intel 852GM GMCH and the Intel ICH4- M. The GMCH integrates the following: • 400-MHz processor Front Side Bus (FSB) controller • Graphics controller interface •... -
Page 22: Processor Interface
System Overview Figure 1. Intel 852GM Chipset System Block Diagram Processor CK-408 400 MHz BPSB 852GM DVOC GMCH 200/266 MHz 732 Micro- FCBGA LVDS Interface 1.5 ATA100 IDE (2) ICH 4-M Wireless (802.11) USB2.0/1.1 (6) 421 BGA Mini-PCI PCI Bus... -
Page 23: Mobile Intel Pentium 4 Processor-M
2.2.3. Intel Celeron M Processor The Intel Celeron M processor utilizes stocketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array(Micro-FCBGA) package technology. The Micro- FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is referred to as the mPGA479M socket. -
Page 24: Intel 852Gm Graphics Memory Controller Hub
• High performance, low power core • Advanced Branch Prediction and Data Prefetch Logic • Advanced Power Management features 2.3. Intel 852GM Graphics Memory Controller Hub 2.3.1. Processor Front Side Bus Support • AGTL+ bus driver technology (gated AGTL+ receivers for reduced power) •... -
Page 25: Packaging/Power
• PCI 2.2 interface (6 PCI Request/Grant Pairs) • Bus Master IDE controller (supports Ultra ATA 100/66/33) • USB 1.1 and USB 2.0 Host Controllers • High Speed Debug port via USB interface • SMBus 2.0 Controller ® Intel 852GM Chipset Platform Design Guide... -
Page 26: Packaging/Power
VCCLAN1_5 (1.5 V LAN logic voltage); VCC3_3 (3.3 V main I/O voltage); VCCSUS3_3 (3.3 V resume I/O voltage); VCCLAN3_3 (3.3 V LAN I/O voltage); V5REF (5 V); V5REF_SUS (5 V); VCCRTC; VCCHI (1.5 V); VCCP (1.2-1.3 V) ® Intel 852GM Chipset Platform Design Guide... -
Page 27: General Design Considerations
Nominal Board Stack-Up The Intel 852GM chipset based platforms require a board stack-up yielding a target impedance of 55 Ω ± 15%. An example of an 8-layer board stack-up is shown in Figure 2. The left side of the figure illustrates the starting dimensions of the metal and dielectric material thickness as well as drawn trace width dimensions prior to lamination, conductor plating, and etching. -
Page 28: Figure 2. Recommended Board Stack-Up Dimensions
The secondary side layer (L8) is also used for power delivery in many cases, since it benefits from the thick copper plating of the external layer plating as well as referencing the close Layer 7 ground plane. The benefit of such a stack-up is low inductance power delivery. ® Intel 852GM Chipset Platform Design Guide... -
Page 29: Alternate Stack Ups
7. If Intel’s recommended stackup guidelines are not implemented, then the OEM is liable for all aspects of their board design and simulations should be performed based on OEM stackup (i.e. - Page 30 General Design Considerations This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 31: Mobile Intel Pentium 4 Processor-M And Mobile Intel Celeron Processor Fsb Design Guidelines
The following layout guidelines support designs using the Mobile Intel Pentium 4 Processor–M / Mobile Intel Celeron Processor and the Intel 852GM chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most FSB signals. -
Page 32: Figure 3. Cross-Sectional View Of 2:1 Ratio
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Parameter Processor Routing Guidelines • An address strobe and its complement should be routed within ± 0.200 of the same Pad-to- ADSTBn/p[1:0]# Pad length. • The pad is defined as the attach point of the silicon die to the package substrate. -
Page 33: Return Path Evaluation
Both recommendations and considerations are presented. For proper operation of the Mobile Pentium 4 Processor-M and the Intel 852GM chipset, it is necessary that the system designer meet the timing and voltage specifications of each component. The following recommendations are Intel’s best guidelines based on extensive simulation and experimentation that... -
Page 34: Source Synchronous (Ss) Signal Group
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines 4.3.1. Source Synchronous (SS) Signal Group Source synchronous groups and associated strobes should be routed on the same layer for the entire length of the bus. This results in a significant reduction of the flight time skew since the dielectric thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup. -
Page 35: Source Synchronous Address Group
3. All traces within each signal group must be routed on the same layer (required). 4. Intel recommends that length of the strobes be centered to the average length of associated data or address traces to maximize setup/hold time margins. -
Page 36: Fsb Data And Address Routing Example
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Figure 5. SS Topology for Address and Data Processor Chip Set 4.3.2. FSB Data and Address Routing Example Figure 6, Figure 7, Figure 8, and Figure 9 provide examples of a board routing for the Data signal group. -
Page 37: Figure 7. Fsb Host Address Routing Example Layer 3
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Figure 7. FSB Host Address Routing Example Layer 3 Layer 3 FSB Address signals Figure 8. FSB Host Data Routing Example Layer 6 Layer 6 FSB Data signals ®... -
Page 38: Figure 9. Fsb Host Address Routing Example Layer 6
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Figure 9. FSB Host Address Routing Example Layer 6 Layer 6 FSB Address signals ® Intel 852GM Chipset Platform Design Guide... -
Page 39: Common Clock (Cc) Agtl+ Signal Group
The Topology 1A OD signals IERR# and FERR# should adhere to the following routing and layout recommendations. Table 5 lists the recommended routing requirements for the IERR# and FERR# signals of the Mobile Intel Pentium 4 Processor–M. The routing guidelines allow the signal to be routed ®... -
Page 40: Topology 1B: Open Drain (Od) Signals Driven By The Processor - Thermtrip
IERR# can be routed as a test point or to any optional system receiver. It is recommended that the FERR# signal of the Intel Mobile Intel Pentium 4 Processor–M be routed to the FERR# signal of the Intel ICH4-M. -
Page 41: Topology 1C: Open Drain (Od) Signals Driven By The Processor - Prochot
Figure 17. Rs should be placed at the beginning of the T-split from the PROCHOT# signal. The pull-up voltage for termination resistor Rtt is VCCP. Intel recommends that PROCHOT# be routed using the voltage translation logic shown in Figure 12. ® Intel... -
Page 42: Topology 2A: Open Drain (Od) Signals Driven By Ich4-M - Pwrgood
Mobile Intel Pentium 4 Processor–M’s PWRGOOD signal. The routing from the Mobile Intel Pentium 4 Processor–M’s PWRGOOD pin should fork out to both to the termination resistor, Rtt, and the ICH4-M. Segments L1 and L2 from Figure 13 should not T-split from a trace from the Mobile Intel Pentium 4 Processor–M pin. -
Page 43: Topology 2B: Cmos Signals Driven By Ich4-M - Dpslp
The routing of DPSLP# at the CPU should fork out to both the ICH4-M and the GMCH. Segments L1 and L2 from Figure 14 should not T-split from a trace from the Mobile Intel Pentium 4 Processor–M pin. -
Page 44: Topology 2C: Cmos Signals Driven By Ich4-M - A20M#, Ignne#, Lint0/Intr, Lint1/Nmi, Slp#, Smi#, And Stpclk
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines 4.3.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# The Topology 2C CMOS A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# signals should implement a point-to-point connection between the ICH4-M and the Mobile Intel Pentium 4 Processor–M. -
Page 45: Itp Debug Port
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Figure 16. Routing Illustration for Topology 3 3.3V V_IO_FWH 3.3V ICH4-M 3904 3904 Table 11. Layout Recommendations for Topology 3 L1 + L2 Transmission Line Type 300 Ω ± 5% 2k Ω... -
Page 46: Logic Analyzer Interface (Lai)
The LAI is installed between the processor socket and the Mobile Intel Pentium 4 Processor–M. The LAI pins plug into the socket, while the Mobile Intel Pentium 4 Processor–M plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile Intel Pentium 4 Processor–M and a logic analyzer. - Page 47 Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Processor lengths GMCH Lengths A[5]# 0.155 HA[5]# A[6]# 0.415 HA[6]# A[7]# 0.304 HA[7]# A[8]# 0.144 HA[8]# A[9]# 0.372 HA[9]# A[10]# 0.327 HA[10]# A[11]# 0.246 HA[11]# A[12]# 0.394...
- Page 48 Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Processor lengths GMCH Lengths D[0]# 0.414 HD[0]# D[1]# 0.475 HD[1]# D[2]# 0.538 HD[2]# D[3]# 0.608 HD[3]# D[4]# 0.386 HD[4]# D[5]# 0.386 HD[5]# D[6]# 0.535 HD[6]# D[7]# 0.464...
- Page 49 Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines Processor lengths GMCH Lengths Data Group 2 DSTBN[2]# 0.252 HDSTBN[2]# DSTBP[2]# 0.266 HDSTBP[2]# D[32]# 0.300 HD[32]# D[33]# 0.226 HD[33]# D[34]# 0.178 HD[34]# D[35]# 0.371 HD[35]# D[36]# 0.271...
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Page 50: Mobile Intel Pentium 4 Processor-M Gtlref Layout And Routing Recommendations
4.5.2. AGTL+ I/O Buffer Compensation The Mobile Intel Pentium 4 Processor–M has 2 pins, COMP[1:0], and the Intel 852GM chipset GMCH has 2 pins, HXRCOMP and HYRCOMP, that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the GMCH requires two special reference voltage generation circuits to pins HXSWING and HYSWING for the ®... -
Page 51: Mobile Intel Pentium 4 Processor-M Agtl+ I/O Buffer Compensation
For the Mobile Intel Pentium 4 Processor–M, the COMP[1:0] pins (see Figure 19) must each be pulled- down to ground with 51.1 Ω ± 1% resistors and should be connected to the Mobile Intel Pentium 4 Processor–M processor with a Zo = 51.1 Ω trace that is less than 0.5 inches from the processor pins. -
Page 52: Intel Celeron M Processor Front Side Bus Design Guidelines
Intel Celeron M Processor Front Side Bus Design Recommendations For proper operation of the Intel Celeron M processor and the GMCH FSB interface, it is necessary that the system designer meet the timing and voltage specification of each component. The following recommendations are Intel’s best guidelines based on extensive simulation and experimentation that... -
Page 53: Trace Space To Trace Width Ratio
For details on minimum motherboard trace length requirements, please refer to Section 4.9.3.3 and Table 13 for more details. Intel recommends routing these signals on the same internal layer for the entire length of the bus. If routing constraints require routing of these signals with a transition to a different layer, a minimum of one ground stitching via for every two signals should be placed within 100 mils of the signal transition vias. -
Page 54: Processor Common Clock Signal Package Length Compensation
Intel Celeron M Processor Front Side Bus Design Guidelines to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the GMCH and the processor package outlines and up to 200 – 300 mils outside the package outline. -
Page 55: Figure 20. Common Clock Topology
Intel Celeron M Processor Front Side Bus Design Guidelines common clock nets on the system board in order to meet the same minimum requirement for trace lengths from the die-pad of the processor to the associated die-pad of the chipset. -
Page 56: Source Synchronous Signals General Routing Guidelines
Intel Celeron M Processor Front Side Bus Design Guidelines 5.4. Source Synchronous Signals General Routing Guidelines All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination resistors connected in a point-to-point, Zo = 55 Ω controlled impedance topology between the processor and the GMCH. -
Page 57: Figure 21. Layer 6 Fsb Source Synchronous Signals Gnd Referencing To Layer 5
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5 In a similar way, Figure 22 illustrates a recommended layout and stack-up example of how another group of FSB source synchronous DATA and ADDRESS signals can reference ground planes on both Layer 2 and Layer 4. -
Page 58: Source Synchronous Signal Length Matching Constraints
5.4.2. Package Length Compensation The Intel Celeron M processor package length does not need to be accounted for in the motherboard routing since the processor has the source synchronous signals and the strobes length matched within the group inside the package routing. However trace length matching of the GMCH package length does need to be accounted for in the motherboard routing since the package does not have the source synchronous signals and the strobes length matched within the group inside the package routing. -
Page 59: Source Synchronous - Data Group
There is some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as secondary operation. -
Page 60: Source Synchronous - Address Group
Intel Celeron M Processor Front Side Bus Design Guidelines Table 16. FSB Source Synchronous Data Signal Routing Guidelines Signal Names Total Trace Length Nominal Spacing Transmission Impedance & Width Line Type Data Data Data Data (Ω) (mils) Group #1 Group #2... -
Page 61: Intel Celeron M Processor And Intel 852Gm Chipset Gmch Fsb Signal Package Lengths
Intel Celeron M Processor and Intel 852GM Chipset GMCH FSB Signal Package Lengths Table 19 lists the preliminary package trace lengths of the Intel Celeron M Processor and the Intel 852GM chipset GMCH for the source synchronous data and address signals. The processor FSB package signals within the same group are routed to the same package trace length, but the GMCH package signals within the same group are not routed to the same package trace length. -
Page 62: Table 19. Intel Celeron M Processor And Gmch Source Synchronous Fsb Signal Package Lengths
Intel Celeron M Processor Front Side Bus Design Guidelines Table 19. Intel Celeron M Processor and GMCH Source Synchronous FSB Signal Package Lengths GMCH GMCH Signal Package GMCH Package Signal Package GMCH Package Signal Signal Group Length Signal Name Length... - Page 63 Intel Celeron M Processor Front Side Bus Design Guidelines GMCH GMCH Signal Package GMCH Package Signal Package GMCH Package Signal Signal Group Length Signal Name Length Group Length Signal Name Length Name Name (mils) (mils) (mils) (mils) DSTBN[2]# HDSTBN[2]# DSTBN[3]#...
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Page 64: Asynchronous Signals
Intel Celeron M Processor Front Side Bus Design Guidelines 5.5. Asynchronous Signals The following sections describe the topologies and layout recommendations for the Asynchronous Open Drain and CMOS signals found on the platform. All Open Drain signals listed in the following sections must be pulled-up to VCCP (1.05 V). -
Page 65: Topology 1A: Open Drain (Od) Signals Driven By The Processor - Ierr
Rtt is VCCP (1.05 V). Intel recommends that the FERR# signal of the processor be routed to the FERR# signal of the ICH4-M. THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the ICH4-M or any optional system receiver. -
Page 66: Topology 1C: Open Drain (Od) Signals Driven By The Processor - Prochot
Intel Celeron M Processor Front Side Bus Design Guidelines If either FERR# or THERMTRIP# is routed to an optional system receiver rather than the ICH4-M and the interface voltage of the optional system receiver does not support a 1.05-V voltage swing, then a voltage translation circuit must be used. -
Page 67: Topology 2A: Open Drain (Od) Signals Driven By Ich4-M - Pwrgood
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 25. Routing Illustration for Topology 1C (System receiver) V_IO_RCVR VCCP 3904 3904 Table 23. Layout Recommendations for Topology 1C Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 k Ω ± 5% 330 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5”... -
Page 68: Topology 2B: Cmos Signals Driven By Ich4-M - Dpslp
Intel Celeron M Processor Front Side Bus Design Guidelines Table 24. Layout Recommendations for Topology 2A Transmission Line Type 330 Ω ± 5% 0.5” – 12.0” 0” – 3.0” Micro-strip 330 Ω ±5% 0.5” – 12.0” 0” – 3.0” Strip-line 5.5.5. -
Page 69: Topology 3: Cmos Signals Driven By Ich4-M To Cpu And Fwh - Init
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 28. Routing Illustration for Topology 2C ICH4-M Table 26. Layout Recommendations for Topology 2C Transmission Line Type 0.5” – 12.0” Micro-strip 0.5” – 12.0” Strip-line 5.5.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH –... -
Page 70: Voltage Translation Logic
In the case of the INIT# signal, resistors with value*s as close as possible to those listed in Figure 30 should be used without exception. With the low 1.05-V signaling level of the Intel Celeron M Processor Front Side Bus, the voltage translation circuit provides ample isolation of any transients or signal reflections at the input of transistor Q1 from reaching the output of transistor Q2. -
Page 71: Processor Reset# Signal
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 30. Voltage Translation Circuit 3.3V 3.3V 330 ohm +/- 5% 1.3K ohm To Receiver +/- 5% 330 ohm 3904 +/- 5% From Driver 3904 5.6. Processor RESET# Signal The RESET# signal is a common clock signal driven by the GMCH CPURST# pin. In a production system where no ITP700FLEX debug port is implemented, a simple point-to-point connection between the CPURST# pin of the GMCH and processor RESET# pin is recommended (see Figure 31). -
Page 72: Processor Reset# Routing Example
Intel Celeron M Processor Front Side Bus Design Guidelines Currently 1% tolerance resistors are recommended for Rs and Rtt. The use of 5% tolerant resistors for these resistors and whether it could provide adequate signal quality performance is under investigation. -
Page 73: Processor And Gmch Host Clock Signals
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 33. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port Secondary Layer 6 GMCH Side GND VIA VCCP ITPFLEX MCH - M Connector RESET# CPURESET# VCCP ITPFLEX CONNECTOR RESET# 5.7. -
Page 74: Processor Gtlref Layout And Routing Recommendations
Processor GTLREF Layout and Routing Recommendations There is one AGTL+ reference voltage pin on the Intel Celeron M Processor, GTLREF, which is used to set the reference voltage level for the AGTL+ signals (GTLREF). The reference voltage must be supplied to the GTLREF pin. The voltage level that needs to be supplied to GTLREF must be equal to 2/3 * VCCP ±... -
Page 75: Figure 35. Processor Gtlref Voltage Divider Network
Do not allow signal lines to use the GTLREF routing as part of their return path (i.e. do not allow the GTLREF routing to create splits or discontinuities in the reference planes of the FSB signals). ® ® RSVD signal pins E26, G1, and AC1 are to be left unconnected on Intel Celeron M processor based systems. -
Page 76: Agtl+ I/O Buffer Compensation
5.9. AGTL+ I/O Buffer Compensation The Intel Celeron M Processor has 4 pins, COMP[3:0], and the GMCH has 2 pins, HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the GMCH requires two special reference voltage generation circuits to pins HSWNG[1:0] for the same purpose described above. -
Page 77: Figure 37. Processor Comp[2] & Comp[0] Resistive Compensation
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 37. Processor COMP[2] & COMP[0] Resistive Compensation COMP[2] COMP[0] 27.4 Ω +/- 1% 27.4 Ω +/- 1% Figure 38. Processor COMP[3] & COMP[1] Resistive Compensation COMP[3] COMP[1] 54.9 Ω +/- 1% 54.9 Ω... -
Page 78: Figure 39. Processor Comp[3:0] Resistor Layout
Intel Celeron M Processor Front Side Bus Design Guidelines Figure 39. Processor COMP[3:0] Resistor Layout COMP[2] COMP[2] COMP[2] COMP[3] COMP[3] COMP[3] COMP[0] pins VCCP VCCP VCCP VCCP VCCP COMP[1] VCCA GND Via VCCA=1.8 SECONDARY SIDE PRIMARY SIDE Figure 40. Processor COMP[1:0] Resistor Alternative Primary Side Layout... -
Page 79: Intel Celeron M Processor Front Side Bus Strapping And Debug Port
Table 29 is applicable only when neither the onboard ITP nor ITP interposer are planned to be used. Intel does not recommend use of the ITP interposer debug port if there is a dependence only on the motherboard termination resistors. The signals below should be isolated from the motherboard via specific termination resistors on the ITP interposer itself per interposer debug port recommendations. -
Page 80: Processor V Ccsense /V
CCSENSE SSSENSE The VCCSENSE and VSSSENSE signals of the Intel Celeron M Processor provide isolated, low impedance connections to the processor’s core power (VCC) and ground (VSS). These pins can be used to sense or measure power (VCC) or ground (VSS) near the silicon with little noise. To make them available for measurement purposes, it is recommended that VCCSENSE and VSSSENSE both be routed with a Zo = 55 Ω... -
Page 81: Processor Power Delivery Requirements
Processor Power Delivery Requirements Processor Power Delivery Requirements Please contact your Intel Field Representative for more information on the electrical requirements for ® ® the DC-to-DC Voltage Regulator for the Mobile Pentium 4 Processor-M featuring Intel SpeedStep technology. ® Intel... - Page 82 Processor Power Delivery Requirements This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 83: System Memory Design Guidelines (Ddr-Sdram)
System Memory Design Guidelines (DDR-SDRAM) The Intel 852GM GMCH chipset Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 30 summarizes the different signal grouping. -
Page 84: Length Matching And Length Formulas
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation is performed as secondary operation. -
Page 85: Topologies And Routing Guidelines
7.3.2. Clock Topology Diagram The Intel 852GM GMCH provides six differential clock output pairs, or three clock pairs per SO-DIMM socket. The motherboard clock routing topology is shown below for reference. Refer to the routing guidelines in Table 2 on the follow page for detailed length and spacing rules for each segment. -
Page 86: Ddr Clock Routing Guidelines
2. The DDR clocks should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all clocks. Surface layer routing should be minimized. ® Intel 852GM Chipset Platform Design Guide... -
Page 87: Clock Length Matching Requirements
25-mil tolerance. Again, the reference length for the two sets of clocks should be offset by the nominal routing length between SO-DIMM connectors. ® Intel 852GM Chipset Platform Design Guide... -
Page 88: Figure 44. Ddr Clock Trace Length Matching Diagram
SCK3 Length = X1 SCK#3 Length = X1 SCK4 SCK4 Length = X1 GMCH SCK4# SCK#4 Length = X1 Length = X1 +/-25mils Note: All lengths are measured from GMCH die-pad to SO-DIMM1 connector pads. ® Intel 852GM Chipset Platform Design Guide... -
Page 89: Clock Package Length Table
The package length data in the table below should be used to tune the motherboard length of each SCLK/SCLK# clock pair between the GMCH and the associated SO-DIMM socket. Intel recommends that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins on the interface. -
Page 90: Clock Routing Updates For "Ddp Stacked" Memory Device Support
S0-DIMM1 7.3.3.4.1. Clock Routing Updates for “DDP Stacked” Memory Device Support Simulation results show that the current DDR layout and routing guidelines for Intel 852GM chipset- based platforms can support “DDP stacked” SO-DIMM memory modules. 7.3.4. Data Signals – SDQ[64:0], SDM[7:0], SDQS[7:0] The GMCH data signals are source synchronous signals that include a 64-bit wide data bus, a set of 8 data mask bits, and a set of 8 data strobe signals. - Page 91 The table and diagrams below depict the recommended topology and layout routing guidelines for the DDR-SDRAM data signals. Intel recommends that the full data bus SDQ[64:0], mask bus SDM[7:0], and strobe signals SDQS[7:0] be routed on the same internal signal layer. It is required that the SDQ byte group and the associated SDM and SDQS signals within a byte lane be routed on the same internal layer.
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Page 92: Data Bus Topology
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR related signals. Data signals should be routed on inner layers with minimized external trace lengths. ® Intel 852GM Chipset Platform Design Guide... -
Page 93: Table 35. Data Signal Group Routing Guidelines
3. It is possible to route using 4 vias if trace segments L2 and L4 are routed on the same external layer as the associated SO-DIMM, for example if L2 is on the same layer as SO-DIMM0. ® Intel 852GM Chipset Platform Design Guide... -
Page 94: Sdqs To Clock Length Matching Requirements
Length matching is only performed from the GMCH to the SO-DIMMs and does not involve the length of L4, which can vary over its entire range. Intel recommends that routing segment length L3 between SO-DIMM0 to SO-DIMM1 be held fairly constant and equal to the offset between clock reference lengths X0 and X1. -
Page 95: Data To Strobe Length Matching Requirements
Y = SDQ, SDM total length, including package length, within same byte lane as show in Figure 48, where: ( X – 25 mils ) ≤ Y ≤ ( X + 25 mils ) ® Intel 852GM Chipset Platform Design Guide... -
Page 96: Sdq To Sdqs Mapping
The following signals are should not be routed out SDQ[71:64], SDM[8], and SDQS[8] as these signals are not supported in the Intel 852GM chipset. Table 36. SDQ/SDM to SDQS Mapping Signal... -
Page 97: Figure 48. Sdq/Sdm To Sdqs Trace Length Matching Diagram
SDQS Length = X SDQ[4] SDQ[5] SDQ Length (Y) = SDQ[6] (X +/-25 mils) SDQ[7] SDM[0] SDM Length (Y) = (X ±25 mils) Note: All lengths are measured from GMCH die- pad to SO-DIMM connector pads. ® Intel 852GM Chipset Platform Design Guide... -
Page 98: Sdq/Sdqs Signal Package Lengths
SDQ_18 SDQ_50 AE24 SDQ_19 AG10 SDQ_51 AH25 SDQ_20 SDQ_52 AG23 SDQ_21 SDQ_53 AF23 SDQ_22 AF10 SDQ_54 AF25 SDQ_23 AE11 SDQ_55 AG25 SDQ_24 AH10 SDQ_56 AH26 SDQ_25 AH11 SDQ_57 AE26 SDQ_26 AG13 SDQ_58 AG28 ® Intel 852GM Chipset Platform Design Guide... - Page 99 AF13 SDQ_62 AE27 SDQ_31 AH13 SDQ_63 AD27 SDM_0 SDQS_0 SDM_1 SDQS_1 SDM_2 SDQS_2 SDM_3 AH12 SDQS_3 AE12 SDM_4 AD19 SDQS_4 AH17 SDM_5 AD21 SDQS_5 AE21 SDM_6 AD24 SDQS_6 AH24 SDM_7 AH28 SDQS_7 AH27 ® Intel 852GM Chipset Platform Design Guide...
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Page 100: Ddr Data Routing Example
7.3.5. Control Signals – SCKE[3:0], SCS#[3:0] The Intel 852GM GMCH chipset control signals, SCKE[3:0] and SCS#[3:0], are clocked into the DDR SDRAM devices using clock signals SCK/SCK#[5:0]. The GMCH drives the control and clock signals together, with the clocks crossing in the valid control window. The GMCH provides one chip select (CS) and one clock enable (CKE) signal per SO-DIMM physical device row. -
Page 101: Control Signal Topology
All internal and external signals should be ground reference to keep the path of return current continuous. Intel suggests that all control signals be routed on the same internal layer. -
Page 102: Control Signal Routing Guidelines
3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel termination resistor. 4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. ® Intel 852GM Chipset Platform Design Guide... -
Page 103: Control To Clock Length Matching Requirements
A nominal CS/CKE package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 852GM Chipset Platform Design Guide... -
Page 104: Figure 51. Control Signal To Clock Trace Length Matching Diagram
CNTRL Length = Y1 GMCH (X1 – 1.0") <= Y1 <= (X1+ 0.5") SCK[4:3] Clock Ref. Length = X1 SCK#[4:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pads. ® Intel 852GM Chipset Platform Design Guide... -
Page 105: Ddr Control Routing Example
System Memory Design Guidelines (DDR-SDRAM) 7.3.5.4. DDR Control Routing Example Figure 52 is an example of a board routing for the Control signal group. Figure 52. Control Signals Group Routing Example From GMCH Control Signals ® Intel 852GM Chipset Platform Design Guide... -
Page 106: Control Group Package Length Table
Rt. Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. -
Page 107: Figure 53. Command Routing For Topology 1
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR related signals. Command signals should be routed on inner layers with minimized external traces. ® Intel 852GM Chipset Platform Design Guide... -
Page 108: Command Topology 1 Routing Guidelines
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. 4. It is possible to route using four vias if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® Intel 852GM Chipset Platform Design Guide... -
Page 109: Command Topology 1 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 852GM Chipset Platform Design Guide... -
Page 110: Figure 54. Topology 1 Command Signal To Clock Trace Length Matching Diagram
RAS#, CAS#, CMD Length = Y1 GMCH (X1 –1.0") <= Y1 <= (X1 +2.0") SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 852GM Chipset Platform Design Guide... -
Page 111: Command Topology 2
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. -
Page 112: Command Topology 2 Routing Guidelines
4. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® Intel 852GM Chipset Platform Design Guide... -
Page 113: Command Topology 2 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 852GM Chipset Platform Design Guide... -
Page 114: Figure 56. Topology 2 Command Signal To Clock Trace Length Matching Diagram
GMCH Package CMD Length = Y1 GMCH (X1 –1.0") <= Y1 <= (X1 +2.0") SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 852GM Chipset Platform Design Guide... -
Page 115: Command Topology 2 Routing Example
System Memory Design Guidelines (DDR-SDRAM) 7.3.6.7. Command Topology 2 Routing Example Figure 57 is an example of a board routing for the Command signal group. Figure 57. Example of Command Signal Group From 852GM Command Signals ® Intel 852GM Chipset Platform Design Guide... -
Page 116: Command Topology 3
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing and minimize trace lengths. All internal and external signals should be ground referenced to keep the path of the return current continuous. -
Page 117: Command Topology 3 Routing Guidelines
4. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that connects to the SO-DIMM1 pad and parallel termination resistor. ® Intel 852GM Chipset Platform Design Guide... -
Page 118: Command Topology 3 Length Matching Requirements
A nominal CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 852GM Chipset Platform Design Guide... -
Page 119: Figure 59. Topology 3 Command Signal To Clock Trace Length Matching Diagram
RAS#, CAS#, CMD Length = Y1 GMCH (X1 –1.0") <= Y1 <= (X1 +2.0") SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 852GM Chipset Platform Design Guide... -
Page 120: Command Group Package Length Table
Table 44. Command Group Package Lengths Signal Pin Number Pkg Length (mils) SMA[0] AC18 SMA[3] AD17 SMA[6] SMA[7] SMA[8] SMA[9] SMA[10] AC19 SMA[11] SMA[12] SBA[0] AD22 SBA[1] AD20 SCAS# AC24 SRAS# AC21 SWE# AD25 ® Intel 852GM Chipset Platform Design Guide... -
Page 121: Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]
• External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths. -
Page 122: Cpc Signal Topology
Figure 61 for details. NOTES: 1. Recommended resistor values and trace lengths may change in a later revision of the design guide. 2. Power distribution vias from Rt to Vtt are not included in this count. ® Intel 852GM Chipset Platform Design Guide... -
Page 123: Cpc To Clock Length Matching Requirements
CPC signals and clock. A nominal CPC package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more details on package length compensation. ® Intel 852GM Chipset Platform Design Guide... -
Page 124: Figure 61. Cpc Signals To Clock Length Matching Diagram
GMCH Package SMAB[5,4,2,1] CPC Length = Y1 GMCH (X1–1.0") <= Y1 <= (X1+0.5") SCK[4:3] Clock Ref Length = X1 SCK#[4:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. ® Intel 852GM Chipset Platform Design Guide... -
Page 125: Cpc Group Package Length Table
7.3.8. Feedback – RCVENOUT#, RCVENIN# The Intel 852GM GMCH provides a feedback signal called “receive enable” (RCVEN#), which is used to measure timing for the read data. In the Intel 852GM GMCH implementation of the GMCH the RCVENOUT# signal is shunted directly to RCVENIN# inside the package in order to reduce timing variance. -
Page 126: External Thermal Sensor Based Throttling (Ets#)
External Thermal Sensor Based Throttling (ETS#) The Intel 852GM chipset GMCH’s ETS# input pin is an active low input that can be used with an external thermal sensor to monitor the temperature of the DDR SO-DIMMs for a possible thermal condition. -
Page 127: Thermal Sensor Placement Guidelines
Sensor location within approx 15mm of SO-DIMM outline will be not be as SO-DIMM outline will be not be as effective at controlling fast transient effective at controlling fast transient temperature changes temperature changes ® Intel 852GM Chipset Platform Design Guide... - Page 128 System Memory Design Guidelines (DDR-SDRAM) This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 129: Integrated Graphics Display Port
1% tolerance that is placed on the circuit board. A reference resistor can be selected from a range between 124 Ω to 137 Ω (1%). The Intel Customer Reference Board uses the value 127 Ω (1%). Based on board design, DAC RGB outputs may be measured when the display is completely white. If the RGB voltage value is between 665 mV to 770 mV, then the video level is within VESA specification and the resistor value that was chosen will be optimal for board design. -
Page 130: Ramdac Board Design Guidelines
Intel recommends that the pi filter and terminating resistors be placed as close as possible to the VGA connector. After the 75-Ohm termination resistor, the RGB signals should continue on to their pi filters and the VGA connector, but should now ideally be routed with a 75-Ohm impedance (~ 5 mil traces). -
Page 131: Ramdac Routing Guidelines
Close proximity to VGA & Docking connectors Place ESD diodes to Do NOT route any high- minimize power rail frequency signals in the inductance – place C1 as shaded area close to diodes as possible ® Intel 852GM Chipset Platform Design Guide... -
Page 132: Figure 64. Ramdac Routing W/ Resistor And Analog Switch Layout Example For Docking Connector
PI-filter and VGA/docking connector. Figure 64. RAMDAC Routing w/ Resistor and Analog Switch Layout Example for Docking Connector Complement DAC Output Intel 852GM Output (e.g. BLUE) (e.g. BLUE#) Via to ground... -
Page 133: Dac Power Requirements
However, since the DAC is an analog circuit, it is particularly sensitive to AC noise seen on its power rail. Designs should provide as clean and quiet a supply as possible to the VCCA_DAC. Additional ® Intel 852GM Chipset Platform Design Guide... -
Page 134: Hsync And Vsync Design Considerations
Integrated Graphics Display Port filtering and/or separate voltage rail may be needed to do so. On the Intel CRB, there is a place holder for a LC filter in case there is noise present in the VCCA power rail. Video DAC Power Supply DC Specification: 1.50 V ± 5% Video DAC Power Supply AC Specification: +/- 0.3% from 0.10 Hz to 10 MHz... -
Page 135: Length Matching Constraints
All length matching formulas are based on GMCH die-pad to LVDS connector pin total length. Package NOTE: length tables are provided for all signals in order to facilitate this pad to pin matching. ® Intel 852GM Chipset Platform Design Guide... -
Page 136: Package Length Compensation
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation is performed as a secondary operation. -
Page 137: Table 52. Lvds Package Lengths
Total Trace Length (mils) ICLKAP 503.7 ICLKAM 498.8 IYAP0 399.6 IYAM0 385.4 IYAP1 487.5 CHANNEL IYAM1 466.2 IYAP2 572.6 IYAM2 566.2 IYAP3 643.2 IYAM3 637.8 ICLKAP 502.0 CHANNEL ICLKAM 499.1 IYBP0 359.8 IYBM0 353.7 ® Intel 852GM Chipset Platform Design Guide... -
Page 138: Digital Video Out Port
TMDS transmitter or integrated TV encoder and TMDS transmitter The Intel 852GM has a single dedicated Digital Video Out Port (DVOC). Intel’s DVO port is a 1.5-V only interface that can support transactions up to 165 MHz. Some of the DVO port command signals may require voltage translation circuit depending on the third party device. -
Page 139: Dvo Port Interface Routing Guidelines
There is of course some overlap in that both affect the target length of an individual signal. Intel recommends that the initial route be completed based on the length matching formulas in conjunction with nominal package lengths and that package length compensation is performed as a secondary operation. -
Page 140: Dvo Routing Guidelines
6 inches. This signal pair should be a minimum of 12 mils from any adjacent signals. • In order to break out of the Intel 852GM GMCH, the DVOC data signals can be routed with a trace width of 4 mils and a trace spacing of 7 mils. The signals should be separated to a trace width of 4 mils and a trace spacing of 8 mils within 0.3 inches of the GMCH component. -
Page 141: Dvo Port Termination
Pull-ups (or pull-ups with the appropriate value derived from simulating the signal) typically ranging from 2.2 kΩ to 10 kΩ are required on each of these signals. The following GMCH signal groups list the six possible GMBUS pairs. ® Intel 852GM Chipset Platform Design Guide... -
Page 142: Leaving The Dvo Port Unconnected
• ADDID[7]: Pulldown to ground with a 1 kΩ resistor when using the DVOC port. This is a vBIOS strapping option to load the TPV AIM module for DVOC port. Pulldown not required DVOC is not enabled. • ADDID[6:0]: Leave unconnected (NC). ® Intel 852GM Chipset Platform Design Guide... -
Page 143: Figure 66. Gvref Reference Voltage
• GVREF: Reference voltage for the DVOC input buffers. Refer to the figure below for proper signal conditioning. Figure 66. GVREF Reference Voltage +V1.5S 1 kΩ 1% GVREF (to DVO device) GVREF(to GMCH) 0.1 µF 0.1 µF 1 kΩ 1% ® Intel 852GM Chipset Platform Design Guide... - Page 144 Integrated Graphics Display Port This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 145: Hub Interface
Table 57. Hub Interface RCOMP Resistor Values Component Trace Impedance HLCOMP Resistor Value HLCOMP Resistor Tied to 55 Ω ± 15% 48.7 Ω ± 1% ICH4-M Vcc1_5 55 Ω ± 15% 27.4 Ω ± 1% GMCH Vcc1_2 ® Intel 852GM Chipset Platform Design Guide... -
Page 146: Hub Interface Data Hl[10:0] And Strobe Signals
HL[10:0] signal must be matched to within ± 100 mils of the strobe signals. All length matching should be done from the Intel 852GM die to the ICH4-M die. Refer to the package length Table 59 and Table 60. -
Page 147: Table 59. Hub Interface Package Lengths For Ich4-M
HUB_PD10 HUB_PD11 HUB_CLK HUB_PSTRB HUB_PSTRB# Table 60. Hub Interface Package Lengths for GMCH Signal Pin Number Package Length (mils) HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] GCLKIN HLSTB HLSTB# ® Intel 852GM Chipset Platform Design Guide... -
Page 148: Terminating Hl[11]
GMCH and ICH4-M. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). If the trace length exceeds 4 inches then the locally generated voltage reference divider should be used. See Section 9.3.2 for the more details. ® Intel 852GM Chipset Platform Design Guide... -
Page 149: Locally Generated Voltage Reference Divider Circuit
(see Table 62). Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). If the voltage specifications are not met then individually generated voltage divider circuit for HIVREF and HI_VSWING is required. ® Intel 852GM Chipset Platform Design Guide... -
Page 150: Gmch Single Generated Voltage Reference Divider Circuit
This option allows for tuning the voltage references HIVREF and HI_VSWING individually. The reference voltage for both HIVREF and HI_VSWING must meet the voltage specification in Table 61. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). ® Intel 852GM Chipset Platform Design Guide... -
Page 151: Separate Gmch Voltage Divider Circuits For Hlvref And Pswing
HLVREF and PSWING must meet the voltage specification in Table 61. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV). Figure 72. Individual HLVREF and PSWING Voltage Reference Divider Circuits for GMCH PSWING HLVREF GMCH ® Intel 852GM Chipset Platform Design Guide... -
Page 152: Hub Interface Decoupling Guidelines
HI side of the capacitors to the V HI power pins. Similarly, if layout allows, metal fingers running on the V HI side of the board should connect the groundside of the capacitors to the V power pins. ® Intel 852GM Chipset Platform Design Guide... -
Page 153: I/O Subsystem
• Grounding: Provide a direct low impedance chassis path between the motherboard ground and hard disk drives. • The ICH4-M Placement: The ICH4-M must be placed equal to or less than 8 inches from the ATA connector(s). ® Intel 852GM Chipset Platform Design Guide... -
Page 154: Primary Ide Connector Requirements
• The 10-k Ω resistor to ground on the PDIAG#/CBLID# signal is required on the Primary Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE interface. ® Intel 852GM Chipset Platform Design Guide... -
Page 155: Secondary Ide Connector Requirements
From a hardware perspective a minimum of two spare control signals (i.e. GPIO’s) and a FET are needed to properly utilize the IDE tri-state feature. An IDE drive must have a reset signal (i.e. first ® Intel 852GM Chipset Platform Design Guide... -
Page 156: Ich4-M Ide Interface Tri-State Feature
IDE channels, respectively. By default, these bits are set to ‘0’ and during normal power-up, should be set to ‘1’ by the BIOS to enable IORDY assertion from the IDE device when an access is requested. ® Intel 852GM Chipset Platform Design Guide... -
Page 157: S5/G3 To S0 Power-Up Procedures For Ide Swap Bay
IDE device once again and waits for the assertion of IORDY in response to an access request. 3. Once the system IDE interface is configured for normal operation once again, the reset signal to the swap device should be deasserted to allow the drive to initialize. ® Intel 852GM Chipset Platform Design Guide... -
Page 158: Pci
The ICH4-M implements an AC’97 2.1, 2.2, and 2.3 compliant digital controller. Please contact your codec IHV (Independent Hardware Vendor) for information on 2.2 compliant products. The AC’97 2.2 specification is on the Intel website: http://developer.intel.com/ial/scalableplatforms/audio/index.htm - 97spec/ The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data streams, as well as control register accesses that employs a time division multiplexed (TDM) scheme. -
Page 159: Figure 76. Ich4-M Ac'97 - Codec Connection
® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)I/O Controller Datasheet . Intel Clocking is provided from the primary codec on the link via AC_BIT_CLK and is derived from a 24.576-MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator requirements. -
Page 160: Figure 77. Ich4-M Ac'97 - Ac_Bit_Clk Topology
47- Ω resistor for R1 was best. 2. Bench data shows that a 47- Ω resistor for R1 is best for the Sigmatel* 9750 codec. Figure 78. ICH4-M AC’97 – AC_SDOUT/AC_SYNC Topology ICH4-M AC_SDOUT Primary Codec ® Intel 852GM Chipset Platform Design Guide... -
Page 161: Figure 79. Ich4-M Ac'97 - Ac_Sdin Topology
Results showed that if the AD1885 codec was used a 33- Ω resistor was best for R1 and if the CS4205b codec was used a 47- Ω resistor for R1 was best. 2. Bench data shows that a 47- Ω resistor for R1 is best for the Sigmatel 9750 codec. ® Intel 852GM Chipset Platform Design Guide... -
Page 162: Ac'97 Routing
Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. • Locate the crystal or oscillator close to the codec. ® Intel 852GM Chipset Platform Design Guide... -
Page 163: Motherboard Implementation
(R ), and the ICH4-M’s integrated pull-down resistor will be read as logic high (0.5 * VCC3_3 to VCC3_3 + 0.5 V). ® Intel 852GM Chipset Platform Design Guide... -
Page 164: Usb 2.0 Guidelines And Recommendations
7. Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0 ® Intel 852GM Chipset Platform Design Guide... -
Page 165: Usb 2.0 Trace Separation
The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6 Ω ± 1% resistor to ground. Place the resistor within 500 mils of the ICH4-M and avoid routing next to clock pins. ® Intel 852GM Chipset Platform Design Guide... -
Page 166: Usb 2.0 Termination
2. All lengths are based upon using a common-mode choke (see Section 10.4.4.1 for details on common-mode choke). 10.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch) The following guidelines apply to the use of plane splits voids and cutouts. ® Intel 852GM Chipset Platform Design Guide... -
Page 167: Vcc Plane Splits, Voids, And Cut-Outs (Anti-Etch)
If the system fuse is rated at 1 amp, then the power carrying traces should be wide enough to carry at least 1.5 amps. ® Intel 852GM Chipset Platform Design Guide... -
Page 168: Emi Considerations
Common mode chokes with a target impedance of 80 Ω to 90 Ω at 100 MHz generally provide adequate noise attenuation. ® Intel 852GM Chipset Platform Design Guide... -
Page 169: Esd
IOAPIC (I/O Advanced Programmable Interrupt Controller) On a Mobile Intel Pentium 4 Processor-M, mobile Intel Celeron Processor and Intel Celeron M Processor based platforms, the serial IOAPIC bus interface of the Intel ICH4-M should be disabled. IOAPIC is supported on the platform and the servicing of interrupts is accomplished via a processor Front Side Bus interrupt delivery mechanism. -
Page 170: Ioapic Disabling Options
IOAPIC Disabling Options 10.5.1.1. Recommended Implementation Intel recommends that IOAPIC be disabled in software while the connections to the board are as shown in Figure 85. Software can be used to turn off PICCLK from clock generator. To disable IOAPIC in BIOS: •... -
Page 171: Smbus Architecture And Design Considerations
Controller SMbus-SMlink_IF Note: Intel does not support external access of the ICH4-M’s Integrated LAN Controller via the SMLink interface. Also, Intel does not support access of the ICH4-M’s SMBus Slave interface by the ICH4-M’s SMBus Host Controller. Refer to the Intel ®... -
Page 172: General Design Issues And Notes
If any physical bus segment exceeds 400 pF, then a bus bridge device like the Phillips* PCA9515 must be used to separate the physical segment into two segments that individually have a bus capacitance less than 400 pF. ® Intel 852GM Chipset Platform Design Guide... -
Page 173: Fwh
Additionally, place a 4.7-µF capacitor between the V supply pins and the V ground pins to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the V supply pins. ® Intel 852GM Chipset Platform Design Guide... -
Page 174: In Circuit Fwh Programming
The FWH INIT# signal trip points need to be considered because they are NOT consistent among different FWH manufacturers. The INIT# signal is active low. Therefore, the inactive state of the Intel ICH4-M INIT# signal needs to be at a value slightly higher than the V min FWH INIT# pin specification. -
Page 175: Fwh V Pp Design Guidelines
This output ball of the ICH4-M is called SUSCLK. This is illustrated in Figure Figure 90. RTCX1 and SUSCLK Relationship in ICH4-M Low-Swing 32.768 kHz RTCX1 Sine Wave Source Internal ICH4-M Oscillator Full-Swing 32.768 kHz SUSCLK Output Signal ® Intel 852GM Chipset Platform Design Guide... -
Page 176: Rtc Crystal
(Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF). 2. V : Power for RTC Well CCRTC 3. RTCX2: Crystal Input 2 – Connected to the 32.7 68-kHz crystal. 4. RTCX1: Crystal Input 1 – Connected to the 32.7 68-kHz crystal. ® Intel 852GM Chipset Platform Design Guide... -
Page 177: External Capacitors
= Crystal’s load capacitance. This value can be obtained from Crystal’s specification. load • C = input capacitances at RTCX1, RTCX2 balls of the ICH4-M. These values can be obtained in the Intel ® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)I/O Controller Datasheet. • C... -
Page 178: Rtc Layout Considerations
To do this, the diodes are set to be reverse biased when the system power is not available. Figure 93 is an example of a diode circuit that is used. ® Intel 852GM Chipset Platform Design Guide... -
Page 179: Rtc External Rtcrst# Circuit
RTC battery life and thereby the RTC accuracy. 10.8.5. RTC External RTCRST# Circuit Figure 94. RTCRST# External Circuit for the ICH4-M RTC CCSUS DIODE/ BATTERY CIRCUIT VccRTC 1.0 µF 180 k RTCRST # 0.1 µF RTCRST# CIRCUIT ® Intel 852GM Chipset Platform Design Guide... -
Page 180: Vbias Dc Voltage And Noise Measurements
RTC. This will prevent these nodes from floating in G3, and correspondingly will prevent I RTC leakage that can cause excessive coin-cell drain. The PWROK input signal should also be configured with an external weak pull-down. ® Intel 852GM Chipset Platform Design Guide... -
Page 181: Internal Lan Layout Guidelines
Internal LAN Layout Guidelines The ICH4-M provides several options for LAN capability. The platform supports several components ® ® depending upon the target market. Available LAN components include the Intel 82562ET, and Intel 82562EM Platform LAN Connect components. Table 74. LAN Component Connections/Features... -
Page 182: Ich4-M - Lan Connect Interface Guidelines
• Direct point-to-point connection between the ICH4-M and the LAN component • LOM Implementation 10.9.1.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET is uniquely installed. Figure 96. Single Solution Interconnect... -
Page 183: Signal Routing And Layout
The following are some general guidelines that should be followed. Intel recommends that the board designer simulate the board routing to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk. -
Page 184: Line Termination
10.9.2. Intel 82562ET / Intel 82562 EM Guidelines For correct LAN performance, designers must follow the general guidelines outlined in Section 10.9.1. Additional guidelines for implementing an Intel 82562ET or Intel 82562EM Platform LAN Connect component are provided below. 10.9.2.1. -
Page 185: Intel 82562Et / Intel 82562Em Termination Resistors
For a noise free and stable operation, place the crystal and associated discrete components as close as possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any noisy signals in this area. -
Page 186: Distance From Magnetics Module To Rj-45 (Distance A)
If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector, distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as short as possible should be a priority. -
Page 187: 10.9.2.5.1. Terminating Unused Connections
10.9.2.5.2. Termination Plane Capacitance Intel recommends that the termination plane capacitance equals a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing. -
Page 188: General Intel 82562Et/82562Em Differential Pair Trace Routing Considerations
10K 5% Intel® 82562EM/ET Disable 10K 5% There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational and disable features for this design. -
Page 189: 10.9.4.1.1. Trace Geometry And Length
Also for similar reasons, traces to I/O signals and signal terminations should be as short as possible. Vias to the ® Intel 852GM Chipset Platform Design Guide... -
Page 190: 10.9.4.1.2. Signal Isolation
To properly implement the common mode choke functionality of the magnetics module the chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100-mils minimum. ® Intel 852GM Chipset Platform Design Guide... -
Page 191: Figure 103. Ground Plane Separation
There should not be a power plane under the magnetics module. ® Intel 852GM Chipset Platform Design Guide... -
Page 192: Common Physical Layout Issues
10. Use of a capacitor that is too large between the transmit traces and/or too much capacitance from the magnetic's transmit center-tap (on the Intel 82562ET side of the magnetics) to ground. Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time so much that they fail the IEEE rise time and fall time specs. -
Page 193: Power Management Interface
AC power and battery power). Droop on this node can potentially cause the CMOS to be cleared or corrupted, the RTC to lose time after several AC/battery power cycles, or the intruder bit might assert erroneously. ® Intel 852GM Chipset Platform Design Guide... -
Page 194: Cpu Cmos Considerations
10.11. CPU CMOS Considerations The Intel 82801DBM ICH4-M has been designed to be voltage compatible with the CMOS signals of the Intel Celeron M processor. For Intel Celeron M Processor based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the V rails for the processor the GMCH. -
Page 195: Figure 105. Ich4-M Cpu Cmos Signals With Cpu And Fwh
I/O Subsystem Figure 105. ICH4-M CPU CMOS Signals with CPU and FWH V_CPU_IO @ 1.05 V FERR# Processor Output Signals ICH4-M ® Intel 852GM Chipset Platform Design Guide... - Page 196 I/O Subsystem This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 197: Platform Clock Routing Guidelines
Table 78 below provides a breakdown of the various individual clocks. Note: When used in Intel 852GM platforms the CK408 is configured in the unbuffered mode and a host clock swing of 710 mV. Table 78. Individual Clock Breakdown... -
Page 198: Clock Group Topologies And Routing Constraints
These topologies and rules have been simulated and verified to produce the required waveform integrity and timing characteristics for reliable platform operation. ® Intel 852GM Chipset Platform Design Guide... -
Page 199: Host Clock Group
The clock synthesizer provides three pairs of 100-MHz differential clock outputs utilizing a 0.7-V voltage swing. The 100-MHz differential clocks are driven to the processor (Mobile Intel Pentium 4 Processor-M, Mobile Intel Celeron processor or Intel Celeron M processor) the GMCH, and the processor debug port with the topology shown in the figure below. -
Page 200: Table 79. Host Clock Group Routing Constraints
1. Differential pairs should be routed as a closely coupled side-by-side pair on a single layer over their entire length. 2. To minimize skew, Intel recommends that all clocks be routed on a single layer. If clock pairs are to be routed on multiple layers, the routed length on each layer should be equalized across all clock pairs. -
Page 201: Host Clock Group General Routing Guidelines
CPU clock pair. Table 80. Clock Package Length Parameter Length Mobile Intel Pentium 4 Processor-M / Mobile Intel 596 mils Celeron Processor Package Length Intel Celeron M Processor Package Length 485 mils... -
Page 202: Clk66 Clock Group
The overall length of CLK66 is considered the reference length for all other clocks, except USBCLK and NOTE: CLK14. The length of this clock should be set within the range and then used as the basis for defining the length of all other length matched clocks. ® Intel 852GM Chipset Platform Design Guide... -
Page 203: Clk33 Clock Group
± 100 mils CLK33 to CLK33 to CLK66 Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 852GM Chipset Platform Design Guide... -
Page 204: Pci Clock Group
PCICLK to PCICLK to (CLK33 – 2.5”) Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 852GM Chipset Platform Design Guide... -
Page 205: Clk14 Clock Group
Clock to Clock Length Matching ± 500 mils CLK14A to CLK14B Breakout Region Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 852GM Chipset Platform Design Guide... -
Page 206: Dotclk Clock Group
Care should be taken to avoid routing through noisy areas and spacing rules should be observed. Guard traces may be employed if necessary with ground stake vias on no less than 0.5- inch intervals. ® Intel 852GM Chipset Platform Design Guide... -
Page 207: Sscclk Clock Group
Total Length Range – L1 + L2 + L3 + L4 3.0” to 8.5” Length Matching Required Breakout Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 852GM Chipset Platform Design Guide... -
Page 208: Usbclk Clock Group
Total Length Range – L1 + L2 3.0” to 12.5” Length Matching Required Breakout Exceptions 5 mil trace with 5 mil space on outers 4 mil trace with 4 mil space in inners Maximum breakout length is 0.3” ® Intel 852GM Chipset Platform Design Guide... -
Page 209: Clock Updates For Intel Celeron M Processor Platforms
CK-408 Clock Updates for Intel Celeron M Processor Platforms To maximize the power savings on Intel Celeron M processor / Intel 852GM Chipset based systems, additional control registers have been added to the CK-408 clock generator to allow option to tri-state the CPU[2:0] host clocks during CPU_STOP# or PWRDWN assertion. - Page 210 Platform Clock Routing Guidelines This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 211: Intel 852Gm Platform Power Delivery Guidelines
12.2. Platform Power Requirements The following figure shows the power delivery architecture for an example of the Intel 852GM chipset platform. To ensure that enough power is available during S3, a thorough power budget should be completed. The power requirements should include each device’s power requirements, S0 – S5. The power requirements should be compared against the power budget supplied by the power supply. -
Page 212: Platform Power Delivery Architectural Block Diagram
Intel 852GM Platform Power Delivery Guidelines The solutions given in this document are only examples. There are many power distribution methods that achieve similar results. It is critical, when deviating from these examples, to consider the effect of the change. -
Page 213: Figure 116. Platform Power Delivery Map For Intel Celeron M Processor
Intel 852GM Platform Power Delivery Guidelines Figure 116. Platform Power Delivery Map for Intel Celeron M Processor Intel® Celeron® M Processor VCC_CORE = IMVP-IV VCCP = IMVP-IV VCCA =+V1.8S 400MHz FSB 852GM GMCH 200/266 MHz VCC-GMCH = 1.35V / 1.2V... -
Page 214: Voltage Supply
HIGH HIGH S3 (STR) HIGH HIGH S4 (STD) HIGH ON/OFF S5 (Soft Off) 12.3.2. Power Supply Rail Descriptions Table 90. Power Supply Rail Descriptions on Intel Reference Board Signal Names Voltage Current Tolerance Enable Description +V1_25S 1.25 0.01 ± 3.2%... -
Page 215: Intel 852Gm Platform Power-Up Sequence
The following sections describe the power-up timing sequence for Intel 852GM GMCH based platforms. 12.4.1. Processor Power Sequence Requirement Contact your Intel Field Representative for details on the Mobile Intel Pentium 4 Processor-M with IMVP-III voltage regulator or Intel Celeron M processor with IMVP-IV voltage regulator. 12.4.2. GMCH Power Sequencing Requirements All GMCH power rails should be stable before PWROK is asserted. -
Page 216: Ich4-M Power Sequencing Requirements
Intel 852GM Platform Power Delivery Guidelines Figure 117. GMCH Power-Up Sequence CPURST# 1ms max RSTIN# 1ms min PWROK GMCH PWR Rails 12.4.3. ICH4-M Power Sequencing Requirements The following figure describes the power-up timing sequence for ICH4-M. The VGATE input should be connected to the processor voltage regulator PWRGD output. -
Page 217: Figure 118. Ich4-M Power-Up Sequence
Intel 852GM Platform Power Delivery Guidelines Figure 118. ICH4-M Power-Up Sequence System S0 state State Hub interface "CPU Reset Complete” Message STPCLK#, STP_CPU#, STP_PCI# SLP_S1#, C3_STAT# T186 T184 Frequency Strap Values Normal Operation Straps T185 PCIRST# T178 T181 SUS_STAT# T177... -
Page 218: 3.3 V/1.5 V Power Sequencing
, or before 5REF within 0.7 V. These rules must be followed in order to ensure the safety of the Intel ICH4-M. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the rail. -
Page 219: 5Refsus Design Guidelines
Intel 852GM Platform Power Delivery Guidelines Figure 119. Example V Sequencing Circuitry 5REF 5REFSUS 12.4.3.3. Design Guidelines 5REFSUS The same rule for V also applies for V . However, in most platforms, the V rail is 5REF 5REF CCSUS3 derived from the V... -
Page 220: Ddr Memory Power Sequencing Requirements
Intel 852GM Platform Power Delivery Guidelines Figure 121. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option +V5S or +V5 Customer specific or Customer specific or +V3ALWAYS Intel recommended Intel recommended USB power circuit USB power circuit V5REF_SUS2 V5REF_SUS1 USB Power (5 V) 0.1 µF... -
Page 221: Intel 852Gm Platform Power Delivery Guidelines
Intel recommends that the developer use the amount of decoupling capacitors specified in this document to ensure the component maintains stable supply voltages. The capacitors should be placed as close to the package as possible. -
Page 222: Gmch Vccsm Decoupling
Intel 852GM Platform Power Delivery Guidelines Table 93. GMCH Decoupling Recommendations Pin Name Configuration TYPE Notes Connect to 0.1 µF XR7, 0603, 16 V, 10% 1 X 0.1 µF within 200 mils VCC1_2S 10 µF XR5, 1206, 6.3 V, 20% 3 X 0.1 µF on bottom side... -
Page 223: Ddr Sdram Vdd Decoupling
• JEDEC Standard, JESD79 (Release 2), Double Data Rate (DDR) SDRAM Specification • Intel DDR 266 JEDEC Spec Addendum Rev 1.0 or later ® Intel... -
Page 224: 2.5-V Power Delivery Guidelines
Intel 852GM Platform Power Delivery Guidelines Figure 123. DDR Power Delivery Block Diagram + V 5 S w itc h in g R e g u la t o r + V 2 _ 5 V in V o u t S e n s e A d j. -
Page 225: Ddr Smrcomp Resistive Compensation
DDR SMRCOMP Resistive Compensation The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer characteristics to specific board and operation environment characteristics. Refer to the RS – Intel ® 852GM GMCH Chipset Datasheet and Figure 124 for details on resistive compensation. The SMRCOMP signal should be routed with as wide a trace as possible. -
Page 226: Ddr Vtt Termination
1.25-V source, VTT, at then end of the memory channel opposite the GMCH. Intel recommends that this VTT be generated from the same source as used for VCCSM, and not be used for GMCH and DDR SMVREF. This is because SMVREF has a much tighter tolerance and VTT can vary more easily depending on signal states. -
Page 227: Figure 126. Gmch Hdvref[2:0] Reference Voltage Generation Circuit
Intel 852GM Platform Power Delivery Guidelines Figure 126. GMCH HDVREF[2:0] Reference Voltage Generation Circuit +VCCP 49.9 852GM GMCH_HDVREF HDVREF0 HDVREF1 HDVREF2 0.1uF Figure 127. GMCH HAVREF Reference Voltage Generation Circuit +VCCP 49.9 852GM GMCH_HAVREF HAVREF 0.1uF Figure 128. GMCH HCCVREF Reference Voltage Generation Circuit +VCCP 49.9... -
Page 228: Figure 129. Primary Side Of The Motherboard Layout
Intel 852GM Platform Power Delivery Guidelines Figure 129. Primary Side of the Motherboard Layout Figure 130. Secondary Side of the Motherboard Layout ® Intel 852GM Chipset Platform Design Guide... -
Page 229: Gmch Agtl+ I/O Buffer Compensation
Intel 852GM Platform Power Delivery Guidelines 12.5.4.2. GMCH AGTL+ I/O Buffer Compensation The HXRCOMP and HYRCOMP pins of the GMCH should each be pulled-down to ground with a 27.4 Ω ± 1% resistor. See Figure 131. The maximum trace length from pin to resistor should be less than 0.5 inches and should be 18-mil wide to achieve the Zo = 27.4 Ω... -
Page 230: Figure 133. Example Analog Supply Filter
Intel 852GM Platform Power Delivery Guidelines VCCALVDS. VCCADAC, VCCAGPLL, and VCCALVDS do not require an RLC filter but do require decoupling capacitors. Figure 133. Example Analog Supply Filter Low Pass Filtering DAMP Filtered V Noise HIGH BULK is not required for all... -
Page 231: Ich4-M Decoupling / Power Delivery Guidelines
Intel recommends that the developer use the amount of high frequency decoupling capacitors specified in table below to ensure that component maintains stable supply voltages. -
Page 232: General Lan Decoupling
Intel 852GM Platform Power Delivery Guidelines 12.5.8. General LAN Decoupling The following are general LAN decoupling recommendations: • All VCC pins should be connected to the same power supply. • All VSS pins should be connected to the same ground plane. -
Page 233: Reserved, Nc, And Test Signals
Intel reserved signals on the processor or GMCH should be handled. The Mobile Intel Pentium 4 Processor–M has a total of eight NC and nine TESTHI signals that are Intel reserved in the pin-map. For connection recommendations on the TESTHI signals, refer to the latest ®... -
Page 234: Intel 852Gm Gmch Rsvd Signals
Intel 852GM GMCH RSVD Signals Intel 852GM has a total of 32 RSVD and 12 NC signals that are Intel reserved in the pin-map. The recommendation is to provide test points for all RSVD signals. All NC signals should be left as no connects. - Page 235 Reserved, NC, and Test Signals Signal Name Ball Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD ® Intel 852GM Chipset Platform Design Guide...
- Page 236 Reserved, NC, and Test Signals This page intentionally left blank. ® Intel 852GM Chipset Platform Design Guide...
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Page 237: Platform Design Checklist
Platform Design Checklist Platform Design Checklist The following checklist provides design recommendations and guidance for the mobile Intel Pentium 4 Processor-M, mobile Intel Celeron processor or Intel Celeron M processor systems with the Intel 852GM chipset platform. It should be used to ensure that design recommendations in this design guide have been followed prior to schematic reviews. -
Page 238: Design Checklist Implementation
4. Vcc1_25 is the 1.25 V VTT rail for DDR. 5. For the Mobile Intel Pentium 4 Processor-M Front Side Bus, VCCP is the 1.2 V-1.3 V. Note that VCCP is the supply to both the Vtt and Vcore for Mobile Intel Pentium 4 Processor-M. -
Page 239: Mobile Intel Pentium 4 Processor-M And Mobile Intel Celeron Processor
Platform Design Checklist 14.4. Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor 14.4.1. Resistor Recommendations Pin Name System Series Voltage Notes Termination Translation Pull-up/Pull-down A20M# Point-to-point connection to ICH4- 220 Ω pull-up to BR0# Point-to-point connection to GMCH, with resistor placed by VCCP GMCH. - Page 240 Connect to VCCP VCCA, VSSA, Connect to VCCP See Figure 136. VCCIOPLL via filter VCCSENSE, Connect to test vias VSSSENSE VSS[182:0] Connect to gnd Default tolerance for resistors is ± 5% unless otherwise specified. NOTE: ® Intel 852GM Chipset Platform Design Guide...
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Page 241: Figure 134. Routing Illustration For Init
3.3V 3.3V +/-5% 1.3K To Receiver +/-5% 3904 +/-5% From Driver 3904 Figure 136. VCCIOPLL, VCCA and VSSA Power Distribution VCCA VCC_VID 4.7uH PLLs 33uF Mother Processor board Core VSSA 33uF VCCIOPLL 4.7uH ® Intel 852GM Chipset Platform Design Guide... -
Page 242: In Target Probe (Itp)
2.5 m Ω. Decoupling guidelines are recommendations based on our reference board design. Customers will need to NOTE: take layout and PCB board design into consideration when deciding on overall decoupling solution. ® Intel 852GM Chipset Platform Design Guide... -
Page 243: Power-Up Sequence
Platform Design Checklist 14.4.4. Power-up Sequence Please refer to processor datasheet for latest information. Table 98. Mobile Intel Pentium 4 Processor-M Power-up Timing Specifications Timing Parameters Unit Notes VccVID active to VID_GOOD µs Please refer to the Mobile Intel Pentium 4 Processor-M Datasheet. -
Page 244: Intel Celeron M Processor
N ote: VID_G O O D is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. For m ore inform ation on im plem entation refer to the Intel M obile Northwood Processor and Intel 845M P Platform R DD P. - Page 245 ICH4-M placed by ICH4-M. THERMTRIP# is a VCCP signal. If connecting to other device, voltage translation logic may be required. VCC[71:0] Connect to VccCORE VCCA[3:0] Connect to Vcc1_8 VCCP[26:0] Connect to VCCP ® Intel 852GM Chipset Platform Design Guide...
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Page 246: Figure 138. Routing Illustration For Init# (For Intel Celeron M Processor)
Connect to gnd Figure 138. Routing Illustration for INIT# (for Intel Celeron M Processor) 3.3V V_IO_FWH 3.3V ICH4-M 3904 3904 Figure 139. Voltage Translation Circuit for PROCHOT# (for Intel Celeron M Processor) 3.3V 3.3V 330ohm +/-5% 1.3K To Receiver +/-5%... -
Page 247: Ck-408 Clock Checklist
Connect to a 14.318 MHz crystal, placed within XTAL_OUT 500 mils of CK-408. VDD[7:0], VDDA Connect to Vcc3_3 Refer to clock vendor datasheet for decoupling info. VSS[5:0], VSSA Connect to gnd VSSIREF Connect to gnd ® Intel 852GM Chipset Platform Design Guide... -
Page 248: Figure 140. Clock Power-Down Implementation
Platform Design Checklist Figure 140. Clock Power-down Implementation VccSus3_3 PM_SLP_S1# CLK_PWRDWN# PM_SLP_S3# ® Intel 852GM Chipset Platform Design Guide... -
Page 249: Intel 852Gm Gmch Checklist
Platform Design Checklist 14.7. Intel 852GM GMCH Checklist 14.7.1. System Memory 14.7.1.1. GMCH System Memory Interface Pin Name System Series Notes Resistor Pull-up/Pull-down RCVENIN# This signal should be routed to a via next to ball and left as a NC (No Connect). -
Page 250: Ddr So-Dimm Interface
Signal can be left as NC (“Not Connected) VDDID Signal can be left as NC (“Not Connected) DU[4:1] Signal can be left as NC (“Not Connected) GND[1:0] Signal can be left as NC (“Not Connected) ® Intel 852GM Chipset Platform Design Guide... -
Page 251: Sodimm Decoupling Recommendation
Signal voltage level = 2/3 of VCCP. Need one 0.1 µF cap and one 1 µF cap for voltage divider. 100 Ω 1% pull-down to gnd Figure 142. Intel 852GM GMCH HXSWING and HYSWING Reference Voltage Generation Circuit +VCCP +VCCP... -
Page 252: Hub Interface
(10 k-100 k). It is up to the DVO device to drive this signal. 100 k Ω pull-down to gnd DVOBCCLKINT Pull-down resistor required only if signal is unused (10 k-100 k). It is up to the DVO device to drive this signal. ® Intel 852GM Chipset Platform Design Guide... -
Page 253: Figure 143. Dpms Clock Implementation
Platform Design Checklist Pin Name System Notes Pull-up/Pull-down DVOBD[11:0] Intel 852GM GMCH supports only one DVO port. So, these signals should be left as NC. DVOBCLK DVOBCLK# DVOBHSYNC DVOBVSYNC DVOBBLANK# DVOBFLDSTL 100 k Ω pull-down to gnd For Intel 852GM GMCH, pull-down resistor (pin M2) required on this signal (10 k-100 k). -
Page 254: Dac
System Notes Pull-up/Pull-down EXTTS 10 k Ω 1% pull-up to Vcc3_3 DPWR# (pin Connect to DPWR# pin of Intel Celeron M processor. AA22) Leave as NC for all other processors. ® ® LCLKCTLB 1 k Ω pull-up to Vcc3_3 for Intel 852GM... -
Page 255: Gmch Decoupling Recommendations
This power signal may be optionally 47 µF connected to Vcc2_5 and powered off in VCCGPIO Connect to Vcc3_3 0.1 µF Bulk decoupling is based on VR solutions used on CRB design. 10 µF ® Intel 852GM Chipset Platform Design Guide... -
Page 256: Gmch Power-Up Sequence
Decoupling guidelines are recommendations based on our reference board design. Customers will need to NOTE: take layout and PCB board design into consideration when deciding on overall decoupling solution. 14.7.7. GMCH Power-up Sequence Table 100. Intel 852GM GMCH Power-up Timing Specifications Timing Parameters Unit Notes PWROK active to RSTIN# inactive. -
Page 257: Ich4-M Checklist
8.2 k Ω pull-up to Vcc3_3 Extneral pull up is required for INT_PIRQE#/GPIO2 INT_PIRQ#[A:D]. External pull up is required INT_PIRQF#/GPIO3 when muxed signal (INT_PIRQ[E:H]#/ INT_PIRQG#/GPIO4 GPIO[2:5]) is implemented as PIRQ. INT_PIRQH#/GPIO5 INT_SERIRQ 8.2 k Ω pull-up to Vcc3_3 ® Intel 852GM Chipset Platform Design Guide... -
Page 258: Gpio
3_3 if signal is required to be pulled-up) • GPIO[28, 27, 25] From resume power well (V Sus3_3). (Note: use V 3_3 if this signal is required to be pulled-up) • These signals are NOT 5-V tolerant. ® Intel 852GM Chipset Platform Design Guide... -
Page 259: Agp_Busy# Design Requirement
This ICH4-M signal requires a pull-up to the switched 3.3-V rail (powered OFF during S3). Vcc3_3 This ICH4-M signal must be connected to the AGP_BUSY# output of GMCH. Please also consult Intel for the latest AGP Busy and Stop signal implementation. NOTE: 14.8.4. (SMBus) System Management Interface Pin Name... -
Page 260: Ac '97 Interface
A series termination resistor is required for the PRIMARY CODEC. One series termination resistor is required for the SECONDARY/ TERTIARY CODEC connector card if the resistor is not found on the connector card. ® Intel 852GM Chipset Platform Design Guide... -
Page 261: Ich4-M Power Management Interface
This signal to ICH4-M should not float. It needs to be at valid level all the time. if not actively driven. 14.8.7. FWH/LPC Interface Pin Name System Notes Pull-up/Pull-down LPC_AD[3:0] No extra pull-ups required. Connect straight to FWH/LPC. ® Intel 852GM Chipset Platform Design Guide... -
Page 262: Usb Interface
R2 = 162 Ω ± 1%, VCCHI=1.5V R3 = 127 Ω ± 1% C1 and C3 = 0.1 µF (near divider) C2, C4, C5, C6 = PVSWING HI_VSWING 0.01µF (near Intel ® component) ICH4 GMCH HIREF HLVREF ® Intel 852GM Chipset Platform Design Guide... -
Page 263: 14.8.10. Rtc Circuitry
R5 = 49.9 Ω ± 1%, R6 = 78.7 Ω ± 1%, R7 = 24.2 Ω ± 1% C1 and C3 = 0.1 µF PVSWING HI_VSWING (near divider) C2, C4, C5, C6 = Intel ® HLVREF HIREF 0.01µF (near GMCH ICH4 component) 14.8.10. -
Page 264: 14.8.11. Lan Interface
Connect to LAN_RXD on the platform LAN Connect Device. LAN_TXD[2:0] If LAN interface is not used, leave the signal unconnected (NC) LAN_RSTYSNC Connect to LAN_RSTSYNC on Platform LAN Connect Devce. If LAN interface is not used, leave the signal unconnected (NC). ® Intel 852GM Chipset Platform Design Guide... -
Page 265: 14.8.12. Primary Ide Interface
(0.5 * Vcc3_3 to Vcc3_3 + 0.5). ® Intel 852GM Chipset Platform Design Guide... -
Page 266: 14.8.15. Ich4-M Decoupling Recommendations
All decoupling guidelines are recommendations based on our reference board design. Customers will need NOTE: to take their layout and PCB board design into consideration when deciding on their overall decoupling solution. Capacitors should be place less than 100 mils from the package. ® Intel 852GM Chipset Platform Design Guide... -
Page 267: Usb Power Checklist
V Vc c c c 5V Sus Distribution 470pF Port 100-150uF Switch G G n n d d Ferrite Bead V V c c c c 470pF Port 100-150uF G G n n d d ® Intel 852GM Chipset Platform Design Guide... -
Page 268: Fwh Checklist
RST# 100 Ω ID[3:0] Signals are recommended to be connected to test points. RSVD[5:1] Signals are recommended to be connected to test points. NC[8:1] The signals should be left as NC (“Not Connected”) ® Intel 852GM Chipset Platform Design Guide... -
Page 269: Lan / Homepna Checklist
0.1 µF VCCP[2:1], VccSus3_3LAN 4.7 µF VCCA[2:1], VCCT[4:1] VCCR[2:1] Connect to 0.1 µF 4.7 uH from power supply to VCCR pins. VccSus3_3LAN via 4.7 µF Caps on VCCR side of the inductor. filter ® Intel 852GM Chipset Platform Design Guide... - Page 270 Platform Design Checklist This page intentionally left blank ® Intel 852GM Chipset Platform Design Guide...
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Page 271: Schematics
Schematics Schematics See the following pages for the reference board schematics. ® Intel 852GM Chipset Platform Design Guide... - Page 272 Mobile Intel Pentium 4 Processor-M / Intel 852GM Chipset CUSTOMER REFERENCE BOARD CK-408 Pentium 4 Header Thermal Test Points Clocking Processor-M PG 38 PG 5 Sensor Clocking PG 36 PG 5 PG 6 478 uFCPGA PG 6 PG 3,4 Montara VR...
- Page 273 Intel 852GM CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION Voltage Rails I C / SMB Addresses Default Jumper Settings Device Address Jumper Default Option Description Page +VDC Primary DC system power supply (10 to 21V) Clock Generator 1101 001x...
- Page 274 H_TCK PM_THRMTRIP# H_VIDPWRGD H_TDI H_VID5 H_TDO TP_CPU_NC4 AE21 H_TMS TRST# H_TRST# 5 Title TP_CPU_NC6 AF24 Mobile Intel Pentium 4 Processor-M 1 of 2 TP_CPU_NC7 TP_CPU_SKTOCC# R1F7 AF25 AF26 SKTOCC# C2D4 Size Project: Document Number Montwood-Processor-MobilSkt 0.1uF Intel 852GM CRB Sheet...
- Page 275 VSS150 VSS71 VSS151 VSS72 VSS152 H_PWRGD 18,37 VSS73 VSS153 VSS74 VSS154 VSS75 VSS155 VSS76 VSS156 VSS77 VSS157 VSS78 VSS158 VSS79 VSS159 VSS80 VSS160 Title Mobile Intel Pentium 4 Processor-M 2 of 2 Size Project: Document Number Intel 852GM CRB Sheet...
- Page 276 R1F8 R1U1 H_BPM4_PRDY# 3 GND1 BPM4# No_Stuff_330 27.4_1% H_BPM5_PREQ# 3 GND2 BPM5# GND3 GND4 GND5 ITP700-FLEXCON Place TCK Title CPU Thermal Sensor & ITP pulldown resistor within 1" of ITP. Size Project: Document Number Intel 852GM CRB Sheet...
- Page 277 PM_SLP_S1# 19,37,38,44 CLKIN SSC_SCLK R2G4 NO_STUFF_0 SCLK LCLKCTLA 7,16 R2G3 SMB_CLK_S 8,11,12,16,18,39 SSC_SDATA R2G6 NO_STUFF_0 LCLKCTLB 7,8,16 SDATA R2G5 SMB_DATA_S 8,11,12,16,18,39 DREFSSCLK CLKOUT REF_OUT 5,8,9,11,15,16,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S DREFSSCLK_D R2G8 REF_OUT ICS91718 Title R2G12 R2G13 CK-408 Size Project: Document Number Intel 852GM CRB...
- Page 278 AJ19 AJ29 RSVD7 MCH_SMVSWINGH 10 SMVSWINGH RVSD7 TP_MCH_NC10 RSVD8 RVSD8 NC10 C5F13 montara-gm C5F6 C5F5 TP_MCH_NC11 RSVD9 RVSD9 NC11 TP_RSVD10 RVSD10 0.1UF 0.1UF 0.1UF RSVD11 RVSD11 montara-gm Title 852GM (1 of 3) Size Project: Document Number Intel 852GM CRB Sheet...
- Page 279 10,18 HUB_PSTRB H_RS#1 PSTRBS RS1# C5T8 C4E5 C4E6 10,18 HUB_PSTRB# PSTRBF RS2# H_RS#2 HUB_HLZCOMP HLZCOMP 0.1UF 0.1UF MCH_PSWING PSWING 10,47 MCH_HLVREF HLVREF Title C6T1 C6T2 montara-gm 852GM (2 of 3) 0.1UF 0.1UF Size Project: Document Number Intel 852GM CRB Sheet...
- Page 280 47uF 22UF 0.1UF 100uF VSS78 VSS163 AB15 VSS79 VSS164 AG15 VSS80 VSS165 5,6,8,11,15,16,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S VSS81 VSS166 VSS82 VSS167 +V3.3S_GMCH_GPIO VSS83 VSS168 R5R6 0.01_1% Title 852GM (3 of 3) C5D8 C5D14 montara-gm Size Project: Document Number 10UF 0.1UF Intel 852GM CRB...
- Page 281 MCH_SMVSWINGL 150_1% MCH_GRCOMP NO_STUFF_470PF MCH_HAVREF MCH_GTLREF2 R6T7 243_1% 9,43,48 +V2.5_GMCH_SM R6T9 NO_STUFF_56.2_1% System Memory C6T5 R6T8 R6T13 8,47 MCH_HLVREF 0.1UF 100_1% Title 60.4_1% R6T11 852GM Circuitry C6T4 R6T10 MCH_SMRCOMP MCH_GTLREF3 60.4_1% Size Project: Document Number Intel 852GM CRB NO_STUFF_0 NO_STUFF_0.01UF...
- Page 282 0.1UF DQS5 DQ61 M_DQS_R6 M_DATA_R_62 DQS6 DQ62 M_DQS_R7 M_DATA_R_63 DQS7 DQ63 M_DQS_R8 DQS8 Layout note: Place capacitors between and near DD R connector if possible SO-DIMM 0 Title DDR SO-DIMMs (1 of 2) Size Project: Document Number Intel 852GM CRB...
- Page 283 M_DATA_R_63 DQS7 DQ63 M_DQS_R8 DQS8 SO-DIMM 1 Layout note: Place capacitors between and near D DR connector if possible SO-DIMM1 is placed further from GMCH than SO-DIMM0 Title DDR SO-DIMMs (2 of 2) Size Project: Document Number Intel 852GM CRB...
- Page 284 M_DM_R_5 RP4G3A M_DM6 M_DM_R_6 RP5G8A RP4G1D 7,12,14 M_CAS# M_CAS_FR# 11 M_DM7 M_DM_R_7 RP5G8D RP4G2C 7,12,14 M_RAS# M_RAS_FR# 11 M_DM8 M_DM_R_8 RP5G8B RP5G5C 7,12,14 M_WE# M_WE_FR# 11 M_DM_R_[8:0] 11,12,14 Title DDR Series Termination Size Project: Document Number Custom Intel 852GM CRB...
- Page 285 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF Title C5W17 C4W7 C5W12 C5W34 C4W5 C5W32 C5W16 C4W4 C6H3 C6H5 C5W7 C5W9 DDR Parallel Termination 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Size Project: Document Number Intel 852GM CRB...
- Page 286 C6D1 0.002_1% ADDDETECT GND7 100uF GND8 22UF 22UF 0.1UF 0.1UF 0.1UF ADD_RSVD_B10 GND9 Note: Intel 852GM does not support ADD_RSVD_A10 GND10 ADD_RSVD_B11 GND11 AGP cards--only AGP Digital Display GND12 cards. DPMS_CLK PIPE# GND13 GND14 ADDID7 should be pulled to 18,22,23,37...
- Page 287 LVDS_BKLTSEL1 34 OE2# R5N1 SMB_DATA_D R5B1 SMB_DATA_S 6,8,11,12,18,39 74CBT3306 J5C1 100K R5N2 NO_STUFF_0 LCLKCTLB 6..8 No Stuff LVDS_BRIGHTNESS LVDS_BKLTEN SMB_CLK_D R5P1 6,8,11,12,18,39 SMB_CLK_S LCLKCTLA R5C2 R5P2 NO_STUFF_0 No Stuff INVERTER CONN 100K Title LVDS Size Project: Document Number Intel 852GM CRB...
- Page 288 24,25 DOCK_QPCIEN# OE1# DAC_QPCIEN C6N3 SOURCE2 NC DOCK_HSYNC DAC_HSYNC OE2# 0.1UF R6B1 DAC_Q_HSYNC DOCK_GREEN 25 SPDT NO_STUFF_3.3pF DOCK_Q_HSYNC DAC_HSYNC NO_STUFF_3.3pF C7B3 C6B4 SN74LVC2G125 DOCK_VSYNC R6N1 NO_STUFF_3.3pF Title DAC (CRT) Connector C6N6 NO_STUFF_3.3pF C6B5 Size Project: Document Number Intel 852GM CRB...
- Page 289 SMB_DATA_S 6,8,11,12,16,39 7,8,10,15,33 PCI_RST# SMB_DATA 21..24,47 +V3.3 15,19,20,23,27,30,32,35,37..39,43,44 INT_APICCLK R6G4 74CBT3306 INT_APICD0 R6G2 INT_APICD1 C8G2 U8G1 R6W2 R6W8 R6W5 0.1UF Title 22..24,26,31,32,34,37 BUF_PCI_RST# ICH4-M (1 of 3) 74AHC1G08 Size Project: Document Number Buffer to reduce loading on PCI_RST# Intel 852GM CRB...
- Page 290 GPIO43 THRMTRIP# TP_GPIO43_D ICH4-M 9,15,20,44,47,48 +V1.5S RTC_RST# RTC_VBIAS R8H1 RTC_X1 C7Y1 10pF RTC_X2 Y7J1 PM_SUS_CLK 15,37 32.768KHZ R7J1 Title ICH4-M (2 of 3) Cap values depend on Xtal Q8H1 SUS_CLK BSS138 Size Project: Document Number Intel 852GM CRB C7J4 10pF...
- Page 291 MAX8888 0.1UF C8H1 0.1UF R8J4 5,15,19,21..23,27..29,32,36..39,44,48 +V3.3ALWAYS 10UF C8J3 20k_1% U7G2D ICH4-M R8J8 R8J10 Q8J3 BSS138 POK_DQ Q8J2 V1.5_PWRGD BSS138 R8J5 POK_D CR8J1A CR8J1B 3904 3904 PM_SLP_S4# 19,32,37,38,43,44 Title ICH4-M (3 of 3) Size Project: Document Number Intel 852GM CRB...
- Page 292 Please place R7F5 C4P2 near C3542 and C4C7 and NO_STUFF_10K U4C2 Pin 9 C3544 near C4P6 near U55A. R4C2 R4C7 GND_V5A FAB ID Strapping Table ICH_FAB_REV BOARD FAB Title ICH4-M Pullups and Testpoints Size Project: Document Number Intel 852GM CRB...
- Page 293 20,21,23,27,36,37,42..44 J7G1 8.2K +V5_PCI 18,19,23 PCI_GNTA# R8N1 PCI_REQA# 18,23 LEGACY HEADER NO_STUFF_0 INT_SERIRQ 18,23,24,32,34,37 FOR ADD-IN 5Pin_Keyed-HDR AUDIO CARD R7V1 TESTING 8.2K VIA SLOT1 ONLY Title PCI Slot 1 & 2 19..21,24,37 +V3.3S_ICH Size Project: Document Number Intel 852GM CRB...
- Page 294 C8C7 C7C5 C7D1 C7E1 C7D7 C8E1 22UF 22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF PCI Slot3 is farthest Title PCI Slot 3/Moon-ISA support & Decoupling from processor Size Project: Document Number Intel 852GM CRB...
- Page 295 +V5S_QSPWR U9C1 18,22,23,26,31,32,34,37 BUF_PCI_RST# C9R2 19,21..23,32,34,37 PM_CLKRUN# DOCK_RESET# 25 0.1UF DOCK_CLKRUN# PCI_GNT4# 18,21 PCI_REQ4# CLK_DOCKPCI DOCK_GNT4# 25 32,36,37 DOCK_INTR# DOCK_REQ4# 25 CLK_DOCKCONNPCI DOCK_DOCKINTR# 1OE# 2OE# Title R9C1 SN74CBTD3384 Docking Q-Switches QUIET DOCK Size Project: Document Number QSWITCH Intel 852GM CRB...
- Page 296 INTA# GND29 LPT_SLCT GND_USB GND21 V_ACDC2 LPT_STB# SUSTAT# UNDKRQ# V_ACDC3 CD4#/GND CD1# 200Pin_Docking-Plug 200Pin_Docking-Plug CR9C1 DOCK_SUSTAT# 19,32,37,38,43,44 PM_SLP_S3# 8,15..18,20,23,24,27,34,35,38..40,42,44,47 +V5S There is pull-up on BAR43 docking station. R9E1 17,24 DOCK_QPCIEN# Title Docking Connector Size Project: Document Number Intel 852GM CRB...
- Page 297 IDE_SDD13 IDE_SDD1 IDE_SDD14 5,6,8,9,11,15,16,18,20,21,23,31,33..36,38..40,42,44,48 +V3.3S IDE_SDD0 IDE_SDD15 RP2J1D IDE_SDDREQ 4.7K IDE_SDIOW# R3J1 IDE_SDIOR# IDE_SD_CSEL IDE_SIORDY IDE_SDDACK# 18,21,37 INT_IRQ15 IDE_SDA1 IDE_SATADET 19,37 IDE_SDA0 R2J1 IDE_SDCS1# IDE_SDACTIVE# 20x2-HDR IDE_SDCS3# IDE_SDA2 Title IDE 1 of 2 Size Project: Document Number Intel 852GM CRB...
- Page 298 AC_RST# 19 2x10-SHD-HDR R9F2 +V5S_IDE_S Layout Note: Place MDC series resistors R2J3 0.1 to 0.4 inches from MDC header based on topology IDE_SDACTIVE#_Q IDE_SDACTIVE# DS2J1 Title GREEN IDE 2 of 2 / MDC INTERPOSER Size Project: Document Number Intel 852GM CRB...
- Page 299 5,15,19..23,27,29,32,36..39,44,48 +V3.3ALWAYS 0.1UF Clamping-Diode Clamping-Diode +V5_ALWAYS 20,21,29 RP4B1C RP4B1D USB_OC2# 19 R4B1 U4B1 FB4B3 50OHM OC1# USBPWR_CONNE USBE_VCC OUT1 Title OUT2 USB (1 of 2) EN_U10 OC2# C4A7 OC2# C4A8 150UF Size Project: Document Number TPS2052 470PF Intel 852GM CRB...
- Page 300 VCC2 BOTTOM CR5M3 CR5M4 C5B4 C5B5 PORT GND11 470PF 150UF STACKED_RJ45_USB Clamping-Diode Clamping-Diode L5M1 USBB- USB_PN4 USBB+ USB_PP4 90@100MHz CR5M1 CR5M2 Clamping-Diode 5,15,19..23,27,28,32,36..39,44,48 +V3.3ALWAYS Clamping-Diode R7V10 USB_OC5# Title USB Connector (2 of 2) Size Project: Document Number Intel 852GM CRB...
- Page 301 Q6A1 are integrated into RJ-45 TESTEN BSS138 18,32 PM_LANPWROK R6M1 Chassis GND Y5A1 (should cover part 82562EM of magnetics) 25MHZ C6A9 C6A8 J6A1 22PF 22PF NO_STUFF 82562EM Testpoint Header Title LAN Interface (82562EM) Size Project: Document Number Intel 852GM CRB...
- Page 302 RSVD2 TP_FWH_RSVD1 TP_FWH_NC1 RSVD1 TP_FWH_RSVD5 TP_FWH_NC2 RSVD5 TP_FWH_RSVD4 TP_FWH_NC3 RSVD4 TP_FWH_RSVD3 TP_FWH_NC4 RSVD3 TP_FWH_NC5 RP9B1B TP_FWH_NC6 GND2 TP_FWH_NC7 GND1 TP_FWH_NC8 GNDA FWH SKT FWH sits in the Title FWH_TSOP_Socket, Size Project: Document Number Not on the board Intel 852GM CRB...
- Page 303 J8B1 BT_DETACH SMB_SC_INT# J9A2 VR_SHUTDOWN_R KSC_RES0 Title KSC_P76 System Management and Keyboard Controller KBC_A20GATE NMI_GATE# SMC_PROG_RST# SMC_MD Size Project: Document Number Note: for flash progamming, must use CON3_HDR Intel 852GM CRB TX1 and RX1, which are pin97 and pin98. CON14_RECEPT...
- Page 304 Q8H3 Q8H4 Q8J1 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10UF 2N3904 2N3904 2N3904 2N3904 Title LED_MUX_HI81 RP9H1A LED_MUX_HI81_D SMC Suspend Timer and Port 80 LEDs LED_MUX_HI80 LED_MUX_HI80_D RP9H1B LED_MUX_LO81 LED_MUX_LO81_D RP9H1C Size Project: Document Number LED_MUX_LO80 LED_MUX_LO80_D RP9H1D Intel 852GM CRB...
- Page 305 C8U6 C8U5 C8F2 R8U3 R8G3 R8G2 NO_STUFF_10K_1% 0.1UF 0.1UF 22UF NO_STUFF_4.7K NO_STUFF_4.7K EV_GPIO_1 DET_1.2V# EV_GPIO_0 R8U2 R8G1 10K_1% NO_STUFF_470 R8G4 Title Super I/O Controller NO_STUFF_470 MontaraGML core voltage detection Size Project: Document Number Intel 852GM CRB Default: Pulled to GND...
- Page 306 MAX3243 R2OUTB is enabled even in suspend. Title R8M1 SER_RIA# is routed to allow the system to Floppy, Parallel, Serial, and IR Ports wake up in Suspend To RAM. Size Project: Document Number Intel 852GM CRB Note: FORCEOFF# overrides FORCEON.
- Page 307 PS/2 keyboard and a 4.7K 4.7K second PS/2 mouse. Otherwise, the keyboard PS/2 connector will only support a PS/2 keyboard. FB1A7 FB1A5 60ohm@100MHz 60ohm@100MHz MOUSE_CLK MOUSE_DATA CP1A1A CP1A1D 47PF 47PF Title Keyboard and Mouse Connectors Size Project: Document Number Intel 852GM CRB...
- Page 308 SMC Sidebands for LPC Power Management J9J3 J7A1 J9E1 J1E2 20..23,27,36,42..44 +V5_LPCSLOT +V3.3 15,18..20,23,27,30,32,35,38,39,43,44 +V3.3_LPCSLOT R9G1 0.01_1% R9G5 0.01_1% Title C9G2 C9G1 C9G4 C8F1 C8F3 C9G3 LPC Slot & Debug Headers 22UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF Size Project: Document Number Intel 852GM CRB...
- Page 309 GREEN Q1G1 BSS138 6,19,37,44 PM_SLP_S1# DS2H2 DS1H2 LED for S3 DS2H1 LED for S5 LED for S4 GREEN GREEN GREEN Q2G3 Title BSS138 Fan Circuit, Test Capacitors and System State LEDs 19,37 PM_SLP_S5# Size Project: Document Number Intel 852GM CRB...
- Page 310 1.050 V 0.625 V 1.000 V 0.600 V 16,21,40,44 +VDC Title 16,21,40,44 +VDC 20x2_Header 20x2_Header Processor VR Interposer Support & Power Circuitry Size Project: Document Number Connector 2 VR Interposer Headers Connector 1 Intel 852GM CRB (rows C,D) (rows A,B)
- Page 311 32,37,39 VR_ON GMCH_VCORE_PWRGD 1.2V_EV 5,6,8,9,11,15,16,18,20,21,23,26,31,33..36,38,39,42,44,48 +V3.3S 5,6,8,9,11,15,16,18,20,21,23,26,31,33..36,38,39,42,44,48 +V3.3S C6C4 0.1UF R6C13 R6C6 1.58K_1% R6C12 VDD+ OPAMP_N U6C2A DELAYED_VR_PWRGD 19,37 TLV2463 OPAMP_EN OPAMP_P Q6C2 C6C5 7,39 IMVP_PWRGD BSS84 R6C8 2K_1% Title IMVP-III VR Controller Size Project: Document Number Intel 852GM CRB...
- Page 312 Processor Decoupling Bulk decoupling values are tuned to Intel’s IMVP III 2 phase VR design. Circuits using other converter topologies may have different requirements. 3..5,9,10,18,20,40,47,48 +VCC_IMVP V_CORE Mid and C3R10 C3T1 C3T4 C3R5 C3D9 C3R8 C3R11 C3R7 C2D2 C3T2 C3R9...
- Page 313 Title Montara-GM VR and VCCP Size Project: Document Number Intel 852GM CRB...
- Page 314 R3V7 19,25,32,37,38,44 PM_SLP_S3# No Stuff R3V6 R3G9 3.92k_1% 0.1UF R3V9 C3V4 VSENSE_2_D C3H1 EV Support Resistor Options 267_1% 8200pF R3V10 NO_STUFF_0 19,20,32,37,38,44 PM_SLP_S4# 0.022uF Title R3V13 DDR VR NO_STUFF_4.99k_1% Vtt Sense Vtt Sense Size Project: Document Number Intel 852GM CRB...
- Page 315 5,15,19..23,27..29,32,36..39,48 +V3.3ALWAYS 1.5V_EV C1D1 Front Panel Connector 22UF U1E2 C1E5 MASTER_RESET# 0.1UF 74AHC1G08 PM_SYSRST# 19 3,5,47 ITP_DBRESET# CON72,RCPTL,TH,700000-668.Normal J1D1 20..23,27,36,37,42,43 +V5_TURNER R1D3 0.01_1% ,35,37..39,43 +V3.3 Title DC/DC Connector +V3.3_TURNER R1D4 0.01_1% 3Pin_RECEPTICLE Size Project: Document Number CON3,RCPTL,TH,700000-667.Normal Intel 852GM CRB...
- Page 316 U4B5 MGM & Core VR VCCP VR PG 39 INTERPOSER_PRES# GMCH_VCORE_PWRGD PG 42 PG 40 U4B3A ON_BOARD_VR_PWRGD U7A5 U4B3B PG 36 PG 36 INTERPOSER_PRES PG 36 U4B3D OFF_BOARD_VR_PWRGD Title Power On Check list Size Project: Document Number Intel 852GM CRB...
- Page 317 PG 22 SLOT PG 5 PG 15 U7A4 PG 33 SMC_RST# MAX809 U8A2 SMC_RES# PG 33 PG 32 PG 32 PG 31 SMC_PROG_RST# H_CPURST# PG 34 H_PWRGD PG 7 PG 3 Title Reset Map Size Project: Document Number Intel 852GM CRB...
- Page 318 PG 33 1.5V PG 45 Scan PG 21 Serial Parallel PG 36 PG 35 PG 35 PG 35 PG 35 Title Block Diagram Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 319 R2T3 Stuffed No_Stuffed S3 (Suspend to RAM) HIGH HIGH S4 (Suspend To Disk) HIGH Title Notes and Annotations Size Project: Document Number S5 / Soft OFF Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 320 A1 and follow-on silicon R2R1 R2R2 R3R2 R3R3 54.9_1% 27.4_1% 54.9_1% 27.4_1% Title Intel Celeron M Processor 1 of 2 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Custom Date: Wednesday, January 12, 2005 Sheet...
- Page 321 VSS92 VSS189 VSS93 VSS190 VSS94 VSS191 R1D6 VSS95 VSS96 Processor-Skt 9,15,19,20,45,46,51 +V1.5S R1D4 NO_STUFF_0 Title Intel Celeron M Processor 2 of 2 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 322 ITP700-FLEXCON Note: C1F2 not needed for Customer Platforms Place TCK Title CPU Thermal Sensor & ITP pulldown resistor within 1" of ITP. Size Project: Document Number Intel Celeron M / 852GM CRB 4.403 C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 323 SMB_CLK_S 8,11,12,16,18 SSC_SDATA R2G8 NO_STUFF_0 SDATA LCLKCTLB 7,8,16 R2G7 SMB_DATA_S 8,11,12,16,18 DREFSSCLK CLKOUT REF_OUT +V3.3S 3,5,8,9,11,15..18,20,21,23,26,31,33..36,38..40,43,45,51 DREFSSCLK_D R2G10 ICS91718 Title R2G12 CK-408 R2G11 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 324 C5F6 C5F5 RSVD9 RVSD9 NC11 TP_RSVD10 RVSD10 0.1UF 0.1UF 0.1UF RSVD11 RVSD11 Intel 852GM Skt Title Intel 852GM GMCH (1 of 3) Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 325 HLZCOMP 0.1UF 0.1UF MCH_PSWING PSWING 10,46 MCH_HLVREF HLVREF Title C6T1 C6T2 Intel 852GM Skt Intel 852GM GMCH (2 of 3) 0.1UF 0.1UF Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 326 VSS165 3,5,6,8,11,15..18,20,21,23,26,31,33..36,38..40,43,45,51 VSS81 VSS166 +V3.3S VSS82 VSS167 +V3.3S_GMCH_GPIO VSS83 VSS168 R5R6 0.01_1% Title Intel 852GM GMCH (3 of 3) C5D8 C5D14 Intel 852GM Skt Size Project: Document Number 0.1UF 10UF Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005...
- Page 327 System Memory C6T5 R6T8 R6T13 8,46 MCH_HLVREF 0.1UF 100_1% 60.4_1% Title R6T11 Intel 852GM GMCH Circuitry C6T4 R6T10 MCH_SMRCOMP MCH_GTLREF3 60.4_1% Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 NO_STUFF_0 NO_STUFF_0.01UF Date: Wednesday, January 12, 2005 Sheet...
- Page 328 DQ63 M_DQS_R8 DQS8 SO-DIMM 0 Layout note: Place capacitors between and near DDR connector if possible. Title DDR SO-DIMMs (1 of 2) Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 329 Layout note: Place capacitors between and near DDR connectors if possible. SO-DIMM 1 is placed farther from the GMCH than SO-DIMM 0 Title DDR SO-DIMMs (2 of 2) Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 330 M_DM_R_7 RP5G8D RP4G2C 7,12,14 M_RAS# M_RAS_FR# 11 M_DM8 M_DM_R_8 RP5G8B RP5G5C 7,12,14 M_WE# M_WE_FR# 11 M_DM_R_[8:0] 11,12,14 Title DDR Series Termination Size Project: Document Number 4.403 Custom Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 331 C5W16 C4W4 C6H3 C6H5 C5W8 C5W9 Title DDR Parallel Termination 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 332 AGP_ST2 GND11 GND12 DPMS_CLK PIPE# GND13 GND14 18,22,23,37 PCI_PME# PME# GND15 GND16 Title AGP Digital Display (ADD) Connector USB- GND17 USB+ GND18 Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 333 NO_STUFF_0 LCLKCTLB 6..8 No Stuff LVDS_BRIGHTNESS LVDS_BKLTEN R5N9 SMB_CLK_D 6,8,11,12,18 SMB_CLK_S LCLKCTLA R5B2 R5N10 NO_STUFF_0 No Stuff INVERTER CONN 100K Title LVDS Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 334 DAC_HSYNC OE2# SPDT NO_STUFF_3.3pF DOCK_Q_HSYNC NO_STUFF_3.3pF C7B2 DAC_Q_HSYNC DAC_HSYNC C6B4 SN74LVC2G125 DOCK_VSYNC 25 R6N1 NO_STUFF_3.3pF Title DAC (CRT) Connector C6N6 NO_STUFF_3.3pF C6B5 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 335 R6G2 INT_APICD1 C8G2 U8G1 R6W2 R6W8 R6W5 0.1UF Title 22..24,26,31,32,34,37 BUF_PCI_RST# ICH4-M (1 of 3) 74AHC1G08 Size Project: Document Number Buffer to reduce loading on PCI_RST# 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 336 Y7J1 PM_SUS_CLK 15,37 32.768KHZ R7J1 Title ICH4-M (2 of 3) Value for C7Y1, C7J4 depends on Xtal Q8H1 SUS_CLK BSS138 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.4031 C7J4 10pF Date: Wednesday, January 12, 2005 Sheet...
- Page 337 ICH4-M R8J8 R8J10 Q8J3 BSS138 POK_DQ Q8J2 V1.5_PWRGD BSS138 R8J5 CR8J1A CR8J1B POK_D 3904 3904 PM_SLP_S4# 19,32,37,38,44,45 Title ICH4-M (3 of 3) Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 338 U4C1 Pin 9 C4B8 near C4C6 near Q4C1A. R4C1 R4C7 GND_V5A FAB ID Strapping Table ICH_FAB_REV BOARD FAB Title ICH4-M Pullups and Testpoints Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 339 NO_STUFF_0 INT_SERIRQ 18,23,24,32,34,37 FOR ADD-IN 5Pin_Keyed-HDR AUDIO CARD R7V1 TESTING 8.2K VIA SLOT1 ONLY Title PCI Slot 1 & 2 +V3.3S_ICH 19..21,24,37 Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 340 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF PCI Slot3 is farthest Title PCI Slot 3/Moon-ISA support & Decoupling from processor Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 341 18,21 PCI_REQ4# CLK_DOCKPCI DOCK_GNT4# 25 32,36,37 DOCK_INTR# DOCK_REQ4# 25 CLK_DOCKCONNPCI DOCK_DOCKINTR# 25 1OE# 2OE# Title R9C1 SN74CBTD3384 Docking Q-Switches QUIET DOCK Size Project: Document Number QSWITCH Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 342 CD1# 200Pin_Docking-Plug 200Pin_Docking-Plug CR9C1 DOCK_SUSTAT# 19,32,37,38,44,45 PM_SLP_S3# 8,15..18,20,23,24,27,34,35,38..41,43,45,46 +V5S There is pull-up on BAR43 docking station. R9E1 17,24 DOCK_QPCIEN# Title Docking Connector Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 343 R3J1 IDE_SDIOR# IDE_SD_CSEL IDE_SIORDY IDE_SDDACK# 18,21,37 INT_IRQ15 IDE_SDA1 IDE_SATADET 19,37 IDE_SDA0 R2J1 IDE_SDCS1# IDE_SDACTIVE# 20x2-HDR IDE_SDCS3# IDE_SDA2 Title IDE 1 of 2 Size Project: Document Number Intel Celeron M / 852GM CRB 4.403 C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 344 0.1 to 0.4 inches from MDC header based on topology IDE_SDACTIVE#_Q IDE_SDACTIVE# DS2J1 Title GREEN IDE 2 of 2 / MDC INTERPOSER Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 345 R4B1 U4B1 FB4B3 50OHM OC1# USBPWR_CONNE USBE_VCC OUT1 Title OUT2 USB (1 of 2) EN_U10 OC2# C4A7 OC2# C4A8 150UF Size Project: Document Number TPS2052 470PF 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 346 Clamping-Diode Clamping-Diode L5M1 USBB- USB_PN4 USBB+ USB_PP4 90@100MHz CR5M2 CR5M1 Clamping-Diode 5,15,19..23,27,28,32,36..39,45,51 +V3.3ALWAYS Clamping-Diode R7V10 USB_OC5# Title USB Connector (2 of 2) Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 347 Chassis GND Y5A1 (should cover part 82562EM of magnetics) 25MHZ C6A9 C6A8 J6A1 22PF 22PF NO_STUFF 82562EM Testpoint Header Title LAN Interface (82562EM) Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 348 TP_FWH_NC4 RSVD3 TP_FWH_NC5 RP9B1B TP_FWH_NC6 GND2 TP_FWH_NC7 GND1 TP_FWH_NC8 GNDA FWH SKT FWH sits in the Title FWH_TSOP_Socket, Size Project: Document Number Not on the board Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 349 System Management and Keyboard Controller KBC_A20GATE NMI_GATE# SMC_PROG_RST# SMC_MD Size Project: Document Number Note: for flash progamming, must use CON3_HDR Intel Celeron M / 852GM CRB C26116 4.403 TX1 and RX1, which are pin97 and pin98. CON14_RECEPT Date: Wednesday, January 12, 2005 Sheet...
- Page 350 2N3904 2N3904 Title LED_MUX_HI81 LED_MUX_HI81_D RP9H1A SMC Suspend Timer and Port 80 LEDs LED_MUX_HI80 LED_MUX_HI80_D RP9H1B LED_MUX_LO81 LED_MUX_LO81_D RP9H1C Size Project: Document Number LED_MUX_LO80 RP9H1D LED_MUX_LO80_D 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 351 SIO_VR_VID5 40 EV_GPIO_0 EV_GPIO_1 DET_1.2V# R8U2 R8G4 R8G1 10K_1% NO_STUFF_470 NO_STUFF_470 Title Super I/O Controller 852GM core Size Project: Document Number voltage detection 4.403 Intel Celeron M / 852GM CRB C26116 Default: Pulled to GND Date: Wednesday, January 12, 2005 Sheet...
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Page 352: Parallel Port
SER_RIA# is routed to allow the system to Floppy, Parallel, Serial, and IR Ports wake up in Suspend To RAM. Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Note: FORCEOFF# overrides FORCEON. Date: Wednesday, January 12, 2005 Sheet... - Page 353 PS/2 keyboard. FB1A7 FB1A5 60ohm@100MHz 60ohm@100MHz MOUSE_CLK MOUSE_DATA CP1A1A CP1A1D 47PF 47PF Title Keyboard and Mouse Connectors Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 354 R9G1 0.01_1% R9G5 0.01_1% Title C9G2 C9G1 C9G4 C8F1 C8F3 C9G3 LPC Slot & Debug Headers 22UF 0.1UF 22UF 0.1UF 0.1UF 0.1UF Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 355 LED for S3 LED for S5 DS2H1 GREEN GREEN Title Q2G3 Fan Circuit, Test Capacitors and System State LEDs BSS138 19,37 PM_SLP_S5# Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 356 16,21,41,43,45 20x2_Header 20x2_Header Title Processor VR Interposer Support & Power Circuitry Size Project: Document Number Connector 1 Connector 2 Intel Celeron M / 852GM CRB C26116 4.403 VR Interposer Headers (rows A,B) (rows C,D) Date: Wednesday, January 12, 2005 Sheet...
- Page 357 R1G2 VR_VID_D4 VR_VID4 SIO_VR_VID4 34 U1F1A LM339 R1F10 C2F5 0.1UF R1G1 VR_VID_D5 VR_VID5 SIO_VR_VID5 34 U1F1B LM339 Title IMVP-IV & Mux Buffer Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 358 Blank Title Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 359 C2R9 C2R6 C2R5 C2R7 C3R16 C2R8 C4D2 150UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF NO_STUFF_150UF Title Processor Decoupling Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
- Page 360 C5C1 needs 20 mil trace no more than 1/2" from pin14 CORE_VR_ON 39 74AHC1G08 R5N11 0 Intel 852GM GMCH VR Controller Title Intel 852GM GMCH VR and VCCP Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403...
- Page 361 VSENSE_2_D C3H1 EV Support Resistor Options 267_1% 8200pF R3V10 NO_STUFF_0 19,20,32,37,38,45 PM_SLP_S4# 0.022uF Title R3V13 DDR VR NO_STUFF_4.99k_1% Vtt Sense Vtt Sense Size Project: Document Number 4.403 Intel Celeron M / 852GM CR C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 362 0.1UF PM_SYSRST# 19 74AHC1G08 3,5,46 ITP_DBRESET# CON72,RCPTL,TH,700000-668.Normal J1D1 20..23,27,36,37,44 +V5_TURNER R1D3 0.01_1% +V3.3 15,18..20,23,27,30,32,35,37,38,44 Title +V3.3_TURNER DC/DC Connector R1D5 0.01_1% 3Pin_RECEPTICLE Size Project: Document Number CON3,RCPTL,TH,700000-667.Normal 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
- Page 363 A_TEMP0N_N EVMC SLOT J1H5 2X5-Header Label on Silk Screen Do Not Use This Slot Title A_TEMP0N_P EVMC SLOT For PCI Operations A_FAN_P0 Size Project: Document Number 4.403 Intel Celeron M / 852GM CRB C26116 Date: Wednesday, January 12, 2005 Sheet...
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Page 364: Power On Sequence
PG 43 INTERPOSER_PRES# PG 39 PG 40 U4B3A ON_BOARD_VR_PWRGD VR_PWRGD U4B3B PG 39 INTERPOSER_PRES PG 39 U4B3D Title OFF_BOARD_VR_PWRGD Power On Check list Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet... - Page 365 U8A2 SMC_RES# PG 33 PG 32 PG 32 PG 31 SMC_PROG_RST# H_CPURST# PG 34 H_PWRGD PG 8 PG 3 Title Reset Map Size Project: Document Number Intel Celeron M / 852GM CRB C26116 4.403 Date: Wednesday, January 12, 2005 Sheet...
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