Intel 855PM Design Manual page 15

R
Tables
Table 1. FSB Common Clock Signal Internal Layer Routing Guidelines ................................ 37
Table 2. FSB Common Clock Signal External Layer Routing Guidelines.............................. 38
Table 3. FSB Data Source Synchronous Signal Trace Length Mismatch Mapping ............... 43
Table 4. FSB Source Synchronous Data Signal Routing Guidelines Topology 1................... 44
Table 5. FSB Source Synchronous Data Signal Routing Guidelines Topology 2................... 44
Table 6. FSB Address Source Synchronous Signal Trace Length Mismatch Mapping......... 45
Table 7. FSB Source Synchronous Address Signal Routing Guidelines ................................ 45
Table 8. Layout Recommendations for Topology 1A .............................................................. 52
Table 9. Layout Recommendations for Topology 1B .............................................................. 53
Table 10. Layout Recommendations for Topology 1C............................................................ 54
Table 11. Layout Recommendations for Topology 2A ............................................................ 55
Table 12. Layout Recommendations for Topology 2B ............................................................ 56
Table 13. Layout Recommendations for Topology 2C............................................................ 58
Table 14. Layout Recommendations for Topology 3 .............................................................. 59
Table 15. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector........ 62
Table 16. ITP Signal Default Strapping When ITP Debug Port Not Used .............................. 74
Table 17. Recommended ITP700FLEX Signal Terminations ................................................. 82
Table 18. Processor and MCH FSB Signal Package Trace Lengths...................................... 89
Table 19. VID vs. V
Table 20. V
Table 21. V
Table 22. V
Table 23. Intel 855PM Chipset DDR Signal Groups ............................................................. 125
Table 24. Data Signal Group Routing Guidelines ................................................................. 127
Table 25. SDQ[71:0] to SDQS[8:0] Length Mismatch Mapping ............................................ 129
Table 26. Control Signal to SO-DIMM Mapping .................................................................... 134
Table 27. Control Signal Routing Guidelines ........................................................................ 135
Table 28. Command Topology 1 Routing Guidelines ........................................................... 140
Table 29. Command Topology 2 Routing Guidelines ........................................................... 145
Table 30. Clock Signal Mapping
Table 31. Clock Signal Group Routing Guidelines................................................................ 150
Table 32. Feedback Signal Routing Guidelines .................................................................... 156
Table 33. Data Signal Group (SDQ[71:0], SDQS[8:0]) Routing Guidelines -
PC2700, PC2100 and PC1600 Compliant ............................................................ 158
Table 34. Existing PC2100/PC1600 DDR SDRAM Design Guidelines Required
for PC2700 Support ............................................................................................... 159
Table 35. Intel 855PM Chipset DDR Signal Package Lengths ............................................. 160
Table 36. AGP 2.0 Signal Groups ......................................................................................... 168
Table 37. AGP 2.0 Data/Strobe Associations ....................................................................... 169
Table 38. Layout Routing Guidelines for AGP 1X Signals .................................................... 170
Table 39. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 172
Table 40. AGP 2.0 Data Lengths Relative to Strobe Length................................................. 172
Table 41. AGP 2.0 Routing Guideline Summary................................................................... 173
Table 42. AGP Pull-Up/Pull-Down Requirements and Straps .............................................. 175
Table 43. AGP 2.0 Pull-up Resistor Values .......................................................................... 175
Table 44. Hub Interface RCOMP Resistor Values ................................................................ 177
Table 45. Hub Interface Signals Internal Layer Routing Summary....................................... 178
Table 46. Hub Interface Signals External Layer Routing Summary...................................... 179
Table 47. Hub Interface HIREF/HI_VSWING Generation Circuit Specifications .................. 180
Table 48. AC'97 AC_BIT_CLK Routing Summary ................................................................ 190
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Intel 855PM Chipset Platform Design Guide
Voltage ......................................................................................... 96
CC-CORE
Decoupling Guidelines
CC-CORE
Decoupling Guidelines .................................................................................. 114
CCP
Decoupling Guidelines.............................................................................. 120
CC-MCH
1 ........................................................................................... 149
........................................................................... 109
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